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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 5: The Clock Module
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
5-186
Offset 0x04,701C
DDS3_CTL
31
Enable
R/W
0
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
30:0
dds3_ctl[30:0]
R/W
0x02F68
4C0
31-bit DDS3 control (default = 20 MHz)
Offset 0x04,7020
DD4_CTL
31
Enable
R/W
0
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
30:0
dds4_ctl[30:0]
R/W
0x02F68
4C0
31-bit DDS4 control (default = 20 MHz)
Offset 0x04,7024
DDS5_CTL
31
Enable
R/W
0
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
30:0
dds5_ctl[30:0]
R/W
0x00E90
452
31-bit DDS5 control (default = 128*48kHz = 6.14 MHz)
Offset 0x04,7028
DDS6_CTL
31
Enable
R/W
0
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
30:0
dds6_ctl[30:0]
R/W
0x04000
000
31-bit DDS6 control (default = 27 MHz)
Offset 0x04,702C
DDS7_CTL
31
Enable
R/W
0
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
30:0
dds7_ctl[30:0]
R/W
0x04000
000
31-bit DDS7 control (default = 27 MHz)
Offset 0x04,7030
DDS8_CTL
31
Enable
R/W
0
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
30:0
dds8_ctl[30:0]
R/W
0x04000
000
31-bit DDS8 control (default = 27 MHz)
Divider Registers: For register 34h power down appropriate clocks before setting these bits
Offset 0x04,7034
CAB_DIVIDER_CTL
31:8
Reserved
R/W
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
8
pd_192
R/W
0
Power down 192 MHz divider in the CAB block.
7
pd_173
R/W
0
Power down 173 MHz divider in the CAB block.
6
pd_157
R/W
0
Power down 157 MHz divider in the CAB block.
5
pd_144
R/W
0
Power down 144 MHz divider in the CAB block.
4
pd_133
R/W
0
Power down 133 MHz divider in the CAB block.
3
pd_123
R/W
0
Power down 123 MHz divider in the CAB block.
2
pd_115
R/W
0
Power down 115 MHz divider in the CAB block.
Table 11: CLOCK MODULE REGISTERS …Continued
Bit
Symbol
Acces
s
Value
Description