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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 8: General Purpose Input Output Pins
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
8-303
4.11 GPIO Interrupt Registers for the FIFO Queues (One for each FIFO
Queue)
Table 17: GPIO Interrupt Registers for the FIFO Queues (One for each FIFO Queue)
Bit
Symbol
Acces
s
Value
Description
Offset 0x10,4FA0+[4*<0-3>]
INT_STATUS<0-3>
31:14
VALID_PTR
R
0
This eld indicates how many valid 32-bit words of data have been
written by the GPIO module to the current DMA buffer:
0x00000 - 1 32-bit word
0x00001 - 2 32-bit words
.....
0x3FFFF - 262143 32-bit words
When a BUFx_RDY signal occurs the address to read from can be
calculated using VALID_PTR. This eld is only updated by the GPIO
after the relevant BUFx_RDY ag is cleared by software.
This eld is valid in Signal Monitoring modes only.
5:4
Reserved
R
0
3
INT_OE
R
0
Internal overrun error. Internal GPIO data buffer has overrun before
data has been written out to external DMA buffer. Data has been
lost.
ONLY USED in signal monitoring modes.
2
FIFO_OE
R
0
FIFO overrun error. A new, empty, DMA buffer was not supplied in
time.
ONLY USED in signal monitoring modes.
1
BUF2_RDY
R
0
-In Signal Monitoring modes: DMA buffer 2 is ready to be read. It is
either full or an interval of silence has occurred.
-In Pattern Generation modes: All contents of DMA buffer 2 have
been read.
0
BUF1_RDY
R
0
-In Signal Monitoring modes: DMA buffer1 is ready to be read. It is
either full or an interval of silence has occurred.
-In Pattern Generation modes: All contents of DMA buffer 1 have
been read.
Offset 0x10,4FA4+[4*<0-3>]
INT_ENABLE<0-3>
31:4
Unused
-
3
INT_OE_EN
R/W
0
Active high Internal overrun error interrupt enable for queue <0-3>.
2
FIFO_OE_EN
R/W
0
Active high FIFO overrun error interrupt enable for queue <0-3>.
1
BUF2_RDY_EN
R/W
0
Active high Buffer 2 ready interrupt enable for queue <0-3>.
0
BUF1_RDY_EN
R/W
0
Active high Buffer 1 ready interrupt enable for queue <0-3>.
Offset 0x10,4FA8+[4*<0-3>]
INT_CLEAR<0-3>
31:4
Unused
-
3
INT_OE_CLR
W
0
Active high internal overrun error interrupt clear for queue <0-3>.
2
FIFO_OE_CLR
W
0
Active high FIFO overrun error interrupt clear for queue <0-3>.
1
BUF2_RDY_CLR
W
0
Active high Buffer 2 ready interrupt clear for queue <0-3>.
0
BUF1_RDY_CLR
W
0
Active high Buffer 1 ready interrupt clear for queue <0-3>.
Offset 0x10,4FAC+[4*<0-3>]
INT_SET<0-3>
31:4
Unused
-