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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 18: SPDIF Input
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
18-578
5
PERR_ENBL
R/W
0
1 = PERR bit in SPDI_STATUS is enabled for interrupts.
0 = PERR bit in SPDI_STATUS is disabled for interrupts.
4
OVR_ENBL
R/W
0
1 = OVERRUN bit in SPDI_STATUS is enabled for interrupts.
0 = OVERRUN bit in SPDI_STATUS is disabled for interrupts.
3
HBE_ENBL
R/W
0
1 = HBE bit in SPDI_STATUS is enabled for interrupts.
0 = HBE bit in SPDI_STATUS is disabled for interrupts.
2
BUF1_ACTIVE_ENBL
R/W
0
1 = BUF1_ACTIVE bit in SPDI_STATUS is enabled for interrupts.
0 = BUF1_ACTIVE bit in SPDI_STATUS is disabled for interrupts.
1
BUF2_FULL_ENBL
R/W
0
1 = BUF2_FULL bit in SPDI_STATUS is enabled for interrupts.
0 = BUF2_FULL bit in SPDI_STATUS is disabled for interrupts.
0
BUF1_FULL_ENBL
R/W
0
1 = BUF1_FULL bit in SPDI_STATUS is enabled for interrupts.
0 = BUF1_FULL bit in SPDI_STATUS is disabled for interrupts.
Offset 0x10 AFE8
SPDI_INTCLR
31:10
Unused
-
9
UNLOCK_CLR
R/W
0
1 = Clear UNLOCK bit in SPDI_STATUS.
0 = No effect
8
UCBITS_CLR
W
0
1 = Clear UCBITS in SPDI_STATUS.
0 = No effect.
7
LOCK_CLR
W
0
1 = Clears LOCK in SPDI_STATUS.
0 = No effect.
6
VERR_CLR
W
0
1 = Clear VERR in SPDI_STATUS.
0 = No effect
5
PERR_CLR
W
0
1 = Clear PERR in SPDI_STATUS.
0 = No effect.
4
OVR_CLR
W
0
1 = Clear OVERRUN in SPDI_STATUS.
0 = No effect.
3
HBE_CLR
W
0
1 = Clear HBE in SPDI_STATUS.
0 = No effect.
2
BUF1_ACTIVE_CLR
W
0
1 = Clear BUF1_ACTIVE in SPDI_STATUS.
0 = No effect.
1
BUF2_FULL_CLR
W
0
1 = Clear BUF2_FULL in SPDI_STATUS.
0 = No effect.
SPDI_BASE1 must be valid before setting BUF2_FULL_CLR.
0
BUF1_FULL_CLR
W
0
1 = Clear BUF1_FULL in SPDI_STATUS.
0 = No effect.
SPDI_BASE1 must be valid before setting BUF1_FULL_CLR.
Offset 0x10 AFEC
SPDI_INTSET
31:10
Unused
-
9
UNLOCK_SET
W
0
1 = UNLOCK bit in SPDI_STATUS is to be set to logic ‘1’. Level
trigger interrupt will be raised to the external interrupt controller if
the corresponding enable bit is set to logic ‘1’.
0 = No effect
Table 6: SPDIF Input Registers …Continued
Bit
Symbol
Acces
s
Value
Description