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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 9: DDR Controller
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
9-340
3:0
ROW_WIDTH
R/W
0xd
Row dimension: 2^ROW_WIDTH rows. I.e., a value of 0xc species
2^12 = 4096 rows. Only the following values are supported:
0x8, 0x9, 0xa, 0xb, 0xc, and 0xd (supporting 256 up to 8192 rows).
Offset 0x06 50D4
RANK1_COLUMN_WIDTH
31:4
Unused
R
-
These bits should be ignored when read, and written as 0’s.
3:0
COLUMN_WIDTH
R/W
0xa
Column dimension: 2^COLUMN_WIDTH columns (each column
has a width of 32 bit). I.e., a value of 0xa species 2^10 = 1024
columns of 32 bit each. Only the following values are supported:
0x8, 0x9, 0xa, and 0xb (supporting 256 up to 2048 columns).
Timing Characteristics
Offset 0x06 5100
DDR_TRCD
31:20
Unused
R
-
These bits should be ignored when read, and written as 0s.
19:16
TRCD_WR
R/W
2
Minimum time between active and write command (RAS to CAS
delay). When the datasheet of the DDR memory does not specify a
value for this timing parameter, use the value as specied for TRCD.
Must be greater or equal than tRAP.
15:4
Unused
R
-
These bits should be ignored when read, and written as 0s.
3:0
TRCD_RD
R/W
4
Minimum time between active and read command (RAS to CAS
delay). When the datasheet of the DDR memory does not specify a
value for this timing parameter, use the value as specied for TRCD.
Must be greater or equal than tRAP.
Offset 0x06 5104
DDR_TRC
31:4
Unused
R
-
These bits should be ignored when read, and written as 0’s.
3:0
TRC
R/W
0xd
Minimum time between two active commands to the same bank.
Offset 0x06 5108
DDR_TWTR
31:4
Unused
R
-
These bits should be ignored when read, and written as 0’s.
3:0
TWTR
R/W
2
Write to read command delay
Offset 0x06 510C
DDR_TWR
31:4
Unused
R
-
These bits should be ignored when read, and written as 0’s.
3:0
TWR
R/W
3
Write recovery time.
Must be greater or equal than tWR_A.
TWR+TRP must be greater or equal than tDAL.
Offset 0x06 5110
DDR_TRP
31:4
Unused
R
-
These bits should be ignored when read, and written as 0’s.
3:0
TRP
R/W
4
Precharge command period.
TWR+TRP must be greater or equal than tDAL.
Offset 0x06 5114
DDR_TRAS
31:4
Unused
R
-
These bits should be ignored when read, and written as 0s.
3:0
TRAS
R/W
9
Minimum delay from active to precharge.
Offset 0x06 511C
DDR_TRRD
31:4
Unused
R
-
These bits should be ignored when read, and written as 0’s.
3:0
TRRD
R/W
2
Active bank a to active bank b command
Table 9: Register Description
Bit
Symbol
Access
Value
Description