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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 30: DCS Network
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
30-822
0
INT_CLR_ENABLE_
ERROR
W
0
Error interrupt enable clear register. This is written by software to
clear the interrupt enable (bit 0 of BC_INT_EN).
1 = Error interrupt enable is cleared
0 = Error interrupt enable is unchanged.
Offset 0x10 3FDC
BC_INT_SET_ENABLE
31:2
Reserved
-
Ignore upon read. Write as zeroes.
1
INT_SET_ENABLE_
TOUT
W
0
Timeout interrupt enable set register. This is written by software to
set the interrupt enable (bit 1 of BC_INT_EN).
1 = Timeout interrupt enable is set
0 = Timeout interrupt enable is unchanged.
0
INT_SET_ENABLE_
ERROR
W
0
Error interrupt enable set register. This is written by software to set
the interrupt enable (bit 0 of BC_INT_EN).
1 = Error interrupt enable is set
0 = Error interrupt enable is unchanged.
Offset 0x10 3FE0
BC_INT_STATUS
31:2
Reserved
-
Ignore upon read. Write as zeroes.
1
INT_STATUS_TOUT
R
0
Timeout interrupt status. Reports any pending timeout interrupts:
1 = Timeout interrupt pending: MMIO bus controller has generated a
timeout because a target has violated the programmable limit for
timeout (see BC_TOUT).
0 = Timeout interrupt is not pending.
0
INT_STATUS_ERROR
R
0
Error interrupt status. Reports any pending error interrupts:
1 = Error interrupt pending, meaning bus controller has detected an
error acknowledge from a target.
0 = Error interrupt is not pending.
Offset 0x10 3FE4
BC_INT_EN
31:2
Reserved
-
Ignore upon read. Write as zeroes.
1
INT_ENABLE_TOUT
R/W
0
Timeout interrupt enable register
1 = Timeout interrupt is enabled
0 = Timeout interrupt is disabled.
0
INT_ENABLE_ERROR
R/W
0
Timeout interrupt enable register
1 = Error interrupt is enabled
0 = Error interrupt is disabled.
Offset 0x10 3FE8
BC_INT_CLR
31:2
Reserved
-
Ignore upon read. Write as zeroes.
1
INT_CLEAR_TOUT
W
0
Timeout interrupt clear register. This is written by software to clear
the interrupt.
1 = Timeout interrupt is cleared
0 = Timeout interrupt is unchanged.
0
INT_CLEAR_ERROR
W
0
Error interrupt clear register. This is written by software to clear the
interrupt.
1 = Error interrupt is cleared
0 = Error interrupt is unchanged.
Table 2:
DCS Controller_TriMedia Conguration Registers (Rev 0.32) …Continued
Bit
Symbol
Acces
s
Value
Description