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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 18: SPDIF Input
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
18-575
7:0
SMASK
R/W
0x00
Allows per bitmasking the least signicant 8 bits of the incoming
samples (corresponding to subframe bits [11:4]). The SMASK
setting only applies to 32-bit capture mode (i.e., SAMP_MODE =
01). The 8 bits of SMASK will determine which subframe bits [11:4]
will be captured and stored in memory.
Note: Setting SMASK[7:0] bits to logic ‘1’ will zero the
corresponding subframe bit [11:4]. Others will pass unchanged.
SPDI_CBITSx Registers
The SPDI_CBITSx registers contain the current block channel status bits. The meaning of each of the channel status elds
can change depending upon whether the input source is a consumer or professional bitstream.
Offset 0x10 A018
SPDI_CBITS1
31:0
CBITS [31:0]
R
0
Channel Status register 1 contains bytes 0, 1, 2 and 3 of the current
Channel Status block according to SPDI_CTL.UCBITS_SEL. It will
always reect the condition of the current decoded block of 192
frames and will always start at the block boundary. Register bit
meaning will depend upon the source transmission (i.e., consumer
vs. professional). See
Table 3 for more details.
Offset 0x10 A01C
SPDI_CBITS2
31:0
CBITS [31:0]
R
0
Channel Status register 2 contains bytes 4, 5, 6 and 7 of the current
Channel Status block according to SPDI_CTL.UCBITS_SEL.
Offset 0x10 A020
SPDI_CBITS3
31:0
CBITS [31:0]
R
0
Channel Status register 3 contains bytes 8, 9,10 and 11 of the
current Channel Status block according to
SPDI_CTL.UCBITS_SEL.
Offset 0x10 A024
SPDI_CBITS4
31:0
CBITS [31:0]
R
0
Channel Status register 4 contains bytes 12, 13, 14 and 15 of the
current Channel Status block according to
SPDI_CTL.UCBITS_SEL.
Offset 0x10 A028
SPDI_CBITS5
31:0
CBITS [31:0]
R
0
Channel Status register 5 contains bytes 16,17,18 and 19 of the
current Channel Status block according to
SPDI_CTL.UCBITS_SEL.
Offset 0x10 A02C
SPDI_CBITS6
31:0
CBITS [191:159]
R
0
Channel Status register 6 contains bytes 20, 21, 22 and 23 of the
current Channel Status block according to
SPDI_CTL.UCBITS_SEL.
SPDI_UBITSx Registers
The SPDI_UBITSx registers contain the current block user data channel bits. The meaning of each of the user data elds is
dependent upon the application.
Offset 0x10 A030
SPDI_UBITS1
31:0
UBITS [31:0]
R
0
User bit 1 contains the state of user bytes 0,1, 2 and 3 of the block
according to SPDI_CTL.UCBITS_SEL. The SPDI_UBITS register
will always reect the condition of the current decoded block of 192
frames. Register bit meaning will depend upon the source
transmission.
Table 6: SPDIF Input Registers …Continued
Bit
Symbol
Acces
s
Value
Description