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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 15: Audio Output
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
15-514
CLOCK_EDGE = 0, the parallel-to-serial converter samples WS on a positive clock
edge transition and outputs the rst bit (bit 0) of a serial frame on the next falling edge
of SCK.
If CLOCK_EDGE = 1, the parallel-to-serial converter samples WS on the negative
edge of SCK, while audio data is output on the positive edge. That is, the SCK
polarity would be reversed with respect to
Figure 3.Every serial frame transmits a single left and right channel sample and optional
codec control data to each D/A converter. The sample data can be in an LSB rst or
MSB rst form at an arbitrary serial frame bit position and with an arbitrary length.
In MSB rst mode (DATAMODE = 0), the parallel-to-serial converter sends the value
of LEFT[MSB] in bit position LEFTPOS in the serial frame. Subsequently, bits from
decreasing bit positions in the LEFT dataword, up to and including LEFT[SSPOS],
are transmitted in order.
In LSB rst mode (DATAMODE = 1), the parallel-to-serial converter sends the value of
LEFT[SSPOS] in bit position LEFTPOS in the serial frame. Subsequent bits from the
LEFT data word, up to and including LEFT[MSB], are transmitted in order. The exact
bits transmitted for a data item ‘S’ are shown in
Table 3.
Frame bits that do not belong to either LEFT[MSB:SSPOS] or RIGHT[MSB:SSPOS]
zero extension ensures that Audio Out can be used in combination with D/A
converters which expect more bits than the actual number of transmitted bits in the
current operating mode (e.g., 18-bit D/As operating with 16-bit memory data).
If a starting position for a eld is dened at a position such that the end of a serial
frame is reached before the end of the data eld is reached, the data beyond the last
bit of the serial frame is truncated.
Figure 3:
Denition of Serial Frame Bit Positions (POLARITY = 1, CLOCK_EDGE = 0)
SCK
WS
SD
framen-1
30
31
0
1
2
3
45
67
8
9
10
11
12
13
14
15
16
17
frame n
18
19
20
21
22
23
24
25
26
27
28 29
30
31
0
1
23
4
5
6
7
frame n+1
Table 3: Bits Transmitted for Each Memory Data Item
Operating Mode
First Bit
Last Bit
Valid SSPOS Values
16 bit/sample, MSB rst
S[15]
S[SSPOS]
0...15
16 bit/sample, LSB rst
S[SSPOS]
S[15]
0...15
32 bit/sample, MSB rst
S[31]
S[SSPOS]
0...31
32 bit/sample, LSB rst
S[SSPOS]
S[31]
0...31