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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 5: The Clock Module
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
5-190
2:1
sel_clk_lan
R/W
00
00: clk_lan = 27 MHz xtal_clk
01: clk_lan = clk_lan_src
10: clk_lan = 27 MHz xtal_clk
11: clk_lan = AO_SD[0]
0
en_clk_lan
R/W
1
1: enable clk_lan
Offset 0x04,711C
CLK_LAN_RX_CTL
31:4
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
3
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
2:1
sel_clk_lan_rx
R/W
00
00: clk_lan_rx = 27 MHz xtal_clk
01: clk_lan_rx = CLK_LAN_RX pin
10: clk_lan_rx = 27 MHz xtal_clk
11: clk_lan_rx = CLK_LAN_RX pin
0
en_clk_lan_rx
R/W
1
1: enable clk_lan_rx
Offset 0x04,7120
CLK_LAN_TX_CTL
31:4
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
3
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
2:1
sel_clk_lan_tx
R/W
00
00: clk_lan_tx = 27 MHz xtal_clk
01: clk_lan_tx = CLK_LAN_TX pin
10: clk_lan_tx = 27 MHz xtal_clk)
11: clk_lan_tx = CLK_LAN_TX pin
0
en_clk_lan_tx
R/W
1
1: enable clk_lan_tx
Offset 0x04,7124
CLK_IIC_CTL
31:4
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
3
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
2:1
sel_clk_iic
R/W
00
00: clk_iic_tx = 27 MHz xtal_clk
01: clk_iic_tx = clk_24
10: clk_iic_tx = 27 MHz xtal_clk
11: clk_iic_tx = AO_SD[1]
0
en_clk_iic
R/W
1
1: enable clk_iic
Offset 0x04,7128
CLK_DVDD_CTL
31:7
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Table 11: CLOCK MODULE REGISTERS …Continued
Bit
Symbol
Acces
s
Value
Description