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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 3: System On Chip Resources
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
3-124
6.3.1
TM3260
System Parameters MMIO Registers
7.
Video Input and Output Routers
PNX15xx/952x Series provides two groups of high speed pins to stream data or video
in and out. The input group of pins is prexed by VDI, Video Data Input. The output
group is prexed by VDO, Video Data Output. Each group is shared between two
modules. On the input side, VIP and FGPI get their pin allocation through the input
router. On the output side QVCP and FGPO get their pin assignment through the
output router. The input router is controlled by VDI_MODE. The output router is
controlled by the VDO_MODE.
Table 7: TM3260 System Parameters MMIO Registers
Bit
Symbol
Acces
s
Value
Description
System Module Registers
Offset 0x06 3700
TM32_CONTROL
31:4
Unused
-
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
3
TM32_APERT_MODIFI
ABLE
R/W
0x1
TM3260 Aperture Modiable.
This bit is usually written once at boot time.
The value of this bit can only be altered once.
0: Disables writes by the TM3260 to the MMIO registers
TM32_DRAM_HI, TM32_DRAM_LO, TM32_APERT_HI and
TM32_APERT_LO.
1: Enables writes by the TM3260 to the MMIO registers
TM32_DRAM_HI, TM32_DRAM_LO, TM32_APERT_HI and
TM32_APERT_LO.
2
TM32_LS_DBLLINE
R/W
0x1
TM3260 Load/Store Unit (i.e. Data Cache) Double Line Fill enable
0: Do not enable Double Line lls for the Load/Store Unit
1: Enable Double Line lls for the Load/Store Unit
1
TM32_IFU_DBLLINE
R/W
0x1
TM3260 Instruction Fetch Unit (i.e. Instruction Cache) Double Line
Fill enable
0: Do not enable Double Line lls for the Instruction Fetch Unit
1: Enable Double Line lls for the Instruction Fetch Unit
0
TM32_PWRDWN_REQ
R/W
0x0
TM3260 full powerdown request
Upon writes:
1->0: Request a TM3260 Power Up
0->1: Request a TM3260 Power Down
Upon reads
Undened
Offset 0x06 3704
TM32_STATUS
31:1
Unused
-
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
0
TM32_PWRDWN_ACK
R
0x0
0: TM3260 is in full power mode.
1: TM3260 is in full powerdown mode.