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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 16: Audio Input
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
16-537
3.6 Memory Buffers and Capture
The Audio Input unit hardware implements a double buffering scheme to ensure that
no samples are lost, even if the chip level controller is highly loaded and slow to
respond to interrupts. The software assigns buffers by writing a base address and
In 16-bit capture modes, the sixteen MSBits of the serial-to-parallel converter output
data are written to memory. In 32-bit capture modes, all bits of the parallel data are
written to memory. If SIGN_CONVERT is set to one, the MSB of the data is inverted,
which is equivalent to translating from two’s complement to offset binary
representation. This allows the use of an external two’s complement 16-32 bit A/D
converter to generate 16-32 bit unsigned samples.
Remark: The Audio In hardware does
not generate A-law or
-law data formats. If
such formats are desired, additional processing is necessary, via software, to convert
from 16-bit linear data to A-law or
-law data.
3.7 Data Bus Latency and HBE
Audio In uses a 128-byte buffer to capture the audio input samples. When 64-bytes of
space is full, the next incoming samples are continuously stored in the remaining
64-byte space while the adapter issues DMA request for the rst 64 bytes of data.
Under normal operation, the rst 64-bytes worth data gets written to memory while
the second 64-bytes worth data is being lled up. This normal operation will be
maintained as long as the data bus arbiter is set to guarantee a latency for Audio In
that matches the incoming audio samples rate.
Given a sample rate
fs, and an associated sample interval T (in nSec), the bus
latency should be at most 16*T nSec in the case of 16 bit samples and 8T nSec in the
case of 32 bit samples, for 2 audio channels. Similarly for 4 channels (8T, 4T), 6
channels (16T/3, 8T/3) and 8 channels (4T, 2T) respectively. If this max latency is not
satised, the HBE (Bandwidth Error) condition will result. This error ag gets set
when the 128-byte buffer is full and a new sample arrives for that buffer. Thus HBE
error condition occurs when the adapter is unable to transfer data from its FIFO to
memory in time. Hence the adapter FIFO gets full and is not able to accommodate
valid data coming from the Audio In block. This results in an HBE condition.
Table 716-bit stereo
- big endian
leftn[15:8]
leftn[7:0]
rightn[15:8] rightn[7:0]
leftn+1[15:8] leftn+1[7:0]
rightn+1[15:8
]
rightn+1[7:0]
32-bit mono -
little endian
leftn[7:0]
leftn[15:8]
leftn[23:16] leftn[31:24] leftn+1[7:0]
leftn+1[15:8]
leftn+1[23:16] leftn+1[31:24]
32-bit mono -
big endian
leftn[31:24] leftn[23:16] leftn[15:8]
leftn[7:0]
leftn+1[31:24
]
leftn+1[23:16
]
leftn+1[15:8]
leftn+1[7:0]
32-bit stereo
- little endian
leftn[7:0]
leftn[15:8]
leftn[23:16] leftn[31:24] rightn[7:0]
rightn[15:8]
rightn[23:16] rightn[31:24]
32-bit stereo
- big endian
leftn[31:24] leftn[23:16] leftn[15:8]
leftn[7:0]
rightn[31:24] rightn[23:16] rightn[15:8]
rightn[7:0]
Table 6: Endian Ordering of Audio Data in Main Memory …Continued
Operating
Modes
m[adr]
m[adr+1]
m[adr+2]
m[adr+3]
m[adr+4]
m[adr+5]
m[adr+6]
m[adr+7]