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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 24: TM3260 Debug
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
24-753
The actual interpretation of the contents of the MMIO registers is determined by a
software protocol used by the debug monitor running on the internal TM3260 CPU
and the debug front-end running on a host machine.
The communication between a host computer and a target system via JTAG requires
the following major components:
1. A Host computer with a serial or parallel interface.
The host computer transfers data to and from the JTAG interface module,
preferably in word-parallel fashion. Also needed is JTAG interface device driver
software to access and modify the registers of the JTAG interface module.
2. A JTAG interface module (hardware) that asynchronously transfers data to and
from the host computer.
The interface module synchronously transfers data to and from the JTAG TAP on
a PNX15xx/952x Series processor, supplies the test clock TCK and other signals
to the JTAG controller on PNX15xx/952x Series. The interface module may be a
PC plug-in board.
This module may transfer data from and to the host computer in bit-serial or
word-parallel fashion. It transfers data from and to the JTAG registers on the
PNX15xx/952x Series processor in bit-serial fashion in accordance with the IEEE
1149.1 Standard. The JTAG interface module connects to a 4 or 5-pin JTAG
connector on the PNX15xx/952x Series board which provides a path to the JTAG
pins on the PNX15xx/952x Series processor. It is the responsibility of the
interface module to scan data in and out of the PNX15xx/952x Series processor
into its internal buffers and make them available to the host computer.
3. A JTAG controller on the PNX15xx/952x Series processor which provides a
bridge between the external JTAG TAP and the internal system.
The controller transfers data from/to the TAP to/from its scannable registers
asynchronous to the internal system clock. A monitor running on the internal
TM3260 CPU and the debugger front-end running on a host computer exchange
data via JTAG by reading/writing the MMIO registers reserved for this purpose,
including two control registers used for handshaking.
4.
Register Descriptions
The PNX15xx/952x Series has two JTAG data registers and two JTAG control
registers (see
Figure 3) in MMIO space and a number of JTAG instructions to
manipulate those registers.
Table 4 lists the MMIO addresses of the JTAG data and
control registers. The addresses are offsets from the MMIO_BASE.
Remark: The sleepless bit is not used in PNX15xx/952x Series.