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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 6: Boot Module
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
6-209
3. Congure the MMI with default DDR SDRAM timing parameter settings that
support as many DRAM vendors as possible. It is recommended to verify these
default parameters comply with the DDR SDRAM devices used to build the
PNX15xx/952x Series system board. Not all the MMI parameters are initialized in
the boot scripts some are the reset defaults of the MMI module. The
Table 3summarizes the values of DDR SDRAM timing parameters once the
congurations of the MMI is completed by the boot. It is then the TM3260 or the
host CPU that is in charge to ne tune these parameters by re-programming the
MMI module according to the DDR SDRAM devices used on the PNX15xx/952x
Series system board. Furthermore ROW_WIDTH and COLUMN_WIDTH have
been set to 11 and 8, respectively, which allows the use of any kind of DDR
SDRAM densities and congurations during the boot process (i.e. in standalone
only 8 Kilobytes of data is written to memory). Finally, some parameters are
dependant on the CAS latency of the devices. After review of different DDR
SDRAM device datasheets, it is found that devices organized in x32 support, at
least, CAS latencies of 3.0. Similarly the devices organized in x16 support at
least a CAS latencies of 2.5. In addition to the CAS latencies the x32 and x16
devices require some different settings for the auto-precharge bit. Therefore
PNX15xx/952x Series BOOT_MODE[3] pin is also used to determine if a x32 or
x16 devices are used in the board system. This assumption is not bullet proof but
works for most of the DDR SDRAM vendors.The boot scripts assume a x32
device when CAS latency is 3.0 and a x16 device when the latency is 2.5.
Table 4 shows the MMI parameters affected by the BOOT_MODE[3] pin, a.k.a.
CAS_LATENCY.
Table 3: Default DDR SDRAM Timing Parameters
Parameter
Value (Clocks)
tRCD read
4
tRCD write
4
tRRD
4
tMRD
4
tWTR
1
tWR
3
tRP
4
tRAS
9
tRFC
15
tRC
13
Table 4: CAS Latency Related DDR SDRAM Timing Parameters
Parameter
CAS_LATENCY = 3.0
CAS_LATENCY = 2.5
PRECHARGE_BIT
8
10
tCAS
6
5