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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 13: FGPO: Fast General Purpose Output
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
13-468
2.4 Record or Message Size
The number of samples per record is set by FGPO_REC_SIZE eld. This is amount
of data that will be output after each record or message start event unless the
FGPO_CTL.VAR_LENGTH bit is set. If the FGPO_CTL.VAR_LENGTH bit is set the
length of a record or message is set by the value of the second 32-bit word read from
the header attached to the record or message.
Valid values are in the range of 2 to 224 - 1.
Remark: The FGPI has a minimum message size of 2 or 3. See FGPI Module
specification for more information.
2.5 Records or Messages Per Buffer
The number of records or messages per buffer is set by FGPO_SIZE register.
Valid values are in the range of 1 to 224 - 1.
2.6 Stride
If the number of records or messages per buffer is greater than one, the address
stride has to be programmed into the FGPO_STRIDE register.
Output starts at a new location in the current buffer on each record or message start
event. After output starts a new address is generated by adding the contents of the
FGPO_STRIDE register to the previous starting address.
Care must be taken that FGPO_STRIDE is greater than or equal to
FGPO_REC_SIZE. Add 8 if either TSTAMP_SELECT or VAR_LENGTH bits are set.
2.7 Interrupt Events
The FGPO_IR_STATUS register contains status and interrupt event status. To
generate an interrupt to the TriMedia processor the corresponding FGPO_IR_ENA bit
must be set. To clear an interrupt event (acknowledge the interrupt) a ‘1’ must be
written to the corresponding FGPO_IR_CLR bit. The FGPO_IR_SET register can be
used to generate software interrupts.
2.7.1
BUF1DONE and BUF2DONE Interrupts
When the number of records or messages output from a main memory buffer equals
the value in the FGPO_SIZE register an associated Buffer Done interrupt will be
generated.
Remark: This interrupt is generated when the FGPO Engine finishes sending the last
sample from the last record/message from the associated main memory buffer.
2.7.2
THRESH1_REACHED and THRESH2_REACHED Interrupts
When FGPO_NRECn (the number of records or messages output from memory
buffer n) equals the contents of the FGPO_THRESHn register then the associated
THRESHn_REACHED bit will be set in the FGPO_IR_STATUS register.