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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 16: Audio Input
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
16-534
Each subsequent clock edge denes a new bit position. Other combinations of
POLARITY and CLOCK_EDGE can be used to dene a variety of serial frame bit
position denitions. Further if the EARLYMODE = 1, then the rst data bit (position 0)
will be the data bit sampled in the same clock edge in which the WS signal transition
The capturing of samples is governed by FRAMEMODE. If FRAMEMODE = 00,
every serial frame results in one sample from the serial-parallel converter. A sample
is dened as a left/right pair in stereo modes or a single left channel value in mono
modes. If FRAMEMODE = 1y, the serial frame data bit in bit position VALIDPOS is
examined. If it has value ‘y’, a sample is taken from the data stream (the valid bit is
allowed to precede or follow the left or right channel data provided it is in the same
serial frame as the data).
The left and right sample data can be in a LSB-rst or MSB-rst form at an arbitrary
bit position and with an arbitrary length. (See
Section 4..) In MSB-rst mode, the
serial-to-parallel converter assigns the value of the bit at LEFTPOS to LEFT[MSB].
Subsequent bits are assigned, in order, to decreasing bit positions in the LEFT data
word, up to and including LEFT[SSPOS]. Bits LEFT[SSPOS–1:0] are cleared. Hence,
in MSB-rst mode, an arbitrary number of bits are captured. They are left-adjusted in
the 16(32)-bit parallel output of the converter.
In LSB-rst mode, the serial to parallel converter assigns the value of the bit at
LEFTPOS to LEFT[SSPOS]. Subsequent bits are assigned, in order, to increasing bit
positions in the LEFT data word, up to and including LEFT[MSB]. Bits LEFT[SSPOS–
1:0] are cleared. Hence, in LSB-rst mode, an arbitrary number of bits are captured.
They are returned left-adjusted in the 16(32)-bit parallel output of the converter.
Figure 3:
Audio In Serial Frame and Bit Position Denition (POLARITY = 1, CLOCK_EDGE = 0, EARLYMODE = 0)
SCK
WS
SD
0
1
2
34
56
7
8
9
10 11
12 13 14 15 16 17 18
frame n
19 20 21 22 23 24 25
26 27
28 29 30 31
0
1
2
3
45
67
frame n+1
Figure 4:
Audio In Serial Frame and Bit Position Denition (POLARITY = 1, CLOCK_EDGE = 0, EARLYMODE = 1)
SCK
WS
SD
0
1
2
34
56
7
8
9
10 11
12 13 14 15 16 17 18
frame n
19 20 21 22 23 24 25
26 27
28 29 30 31
0
1
2
3
45
67
frame n+1