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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
21-666
2
Bitstream error
R/W
0
Logic ‘1’ indicates VLD encountered an illegal Huffman code or an
details on the error handling procedure.
This bit is cleared by writing a logic ‘1’ to it.
1
Start code detected
R/W
0
Logic ‘1’ indicates VLD encountered 0x000001 while executing
current command.
This bit is cleared by writing a logic ‘1’ to it.
0
VLD Command done
R/W
0
Logic ‘1’ indicates successful completion of current command.
This bit is cleared by issuing a new command.
Offset 0x07 5014
VLD_IE
31:16
Reserved
15:8
Reserved
-
7:0
VLD Int. Enables
R/W
0
Each of these bits enables the matching bit from the VLD_STATUS
reg 0x010 to issue an IR to the CPU.
Offset 0x07 518
VLD_CTL
31:17
Reserved
16
slice_start_code_strobe
R/W
0
When CPU writes 1 into this eld, VLD copies the value of
slice_start_code into its internal register. CPU should do this only
when the VLD is stopped. This bit is always read as 0.
15:8
slice_start_code
R/W
0
Slice start code when the VLD is restarted; the
slice_start_code_strobe bit field must be set to ‘1’ in order to update
this eld.
7:3
Reserved
2
DMA-input-done-mode
R/W
0
When this bit is ‘0’, VLD sets the DMA_INPUT_DONE ag (in
VLD_MC_STATUS register) when the DMA_INP_CNT transitions
from non-zero to zero.
When this bit is ‘1’, the same ag is set only with the additional
condition that both highway input buffers are empty.
The slice_start_code_strobe bit eld must be set to ‘0’ in order to
update this eld)
1
Reserved
0
Little_Endian
R/W
1
Force the VLD to operate in Little Endian mode when ‘1’. When set
to ‘0’ the VLD operates in Big Endian mode. The
slice_start_code_strobe bit must be set to ‘0’ in order to update this
bit.
Offset 0x07 501C
VLD_INP_ADR
31:0
VLD Input Memory
Address
R/W
0
Memory address from which VLD is reading (updated when DMA
read transfer is completed). Must be 32-bit word aligned.
Offset 0x07 5020
VLD_INP_CNT
31:15
Reserved
14:0
VLD Input Count
R/W
0
Number of bytes to be read from main memory
Offset 0x07 5024
VLD_MBH_ADR
31:0
MB Header Memory
Address
R/W
0
Memory address to which the VLD writes macroblock headers when
VLD_CTL[1] is set. Must be 32-bit word aligned.
Table 10: VLD Registers …Continued
Bit
Symbol
Acces
s
Value
Description