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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 11: QVCP
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
11-375
3.
Programming and Resource Assignment
3.1 MMIO and Task Based Programming
In order for the QVCP to function properly its various block have to be congured.
Each functional unit contains a set of programming registers. A more detailed
description of the various registers can be found in the register description section of
this document.
The registers are divided in layer specic registers and global registers. Layer specic
registers are used to set up the layer related functions such as layer position, size,
pixel format and various conversion functions. The global register space
accommodates functions such as screen timing and output format related functions.
Another important part of the global register space are the resource assignment
registers which allow to assign the pool resources to specic layers.
There are two ways to access the QVCP registers:
1. The rst and primary way to get read/write access to the registers is via the
MMIO bus, which maps the registers into the overall PNX15xx/952x Series
address space.
2. The second way to get write-only access to the registers is via data structures
fetched through the VBI DMA access port (used to fetch VBI data which get
inserted into the output data stream). Differentiation between VBI and
programming data is accomplished via a different header.
The data structure to be used contains a header consisting of a pointer to the next
packet in memory. A null pointer indicates the last packet in a linked list. The header
also contains a eld ID eld which allows eld synchronized insertion of VBI or re-
programming packets. Packet insertion can cause an interrupt if the appropriate
header ag is set. A detailed view of the packet format can be found in
Figure 7.Each data packet consists of an 8-byte descriptor followed by data (see
Table 5.)Table 5: Data Packet Descriptor
Bit
Description
12:0
Data byte count
13
Unused
14
1=wait for proper vertical eld
0=send data on current eld without considering the eld ID (for a series of packets to
be inserted in the same eld, this bit should only be set for the rst packet and not for
subsequent ones. If this bit is set for all packets, they will be inserted with one eld
delay each).
15
1=generate interrupt when this packet is transmitted
0=don’t generate packet interrupt
27:16
Screen line in which to insert the data packet
0=rst line after rising edge of VSYNC
0xFFF=line compare disabled. The packet is inserted without consideration of the
line counter.
30:28
Field ID for this packet to be sent on