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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 8: General Purpose Input Output Pins
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
8-295
15:4
INTERVAL
R/W
0
Interval of silence. If a change is monitored on a signal and no more
signal activity is monitored for a time equal to the interval of silence,
writing to the current buffer is halted and a BUFx_RDY interrupt is
generated. Writing continues to the alternate buffer.
This eld is only valid if FIFO_MODE[1:0] = 00.
0x000 - Disabled
0x001 - 1x128 13.5 MHz period, 9.48
s
0x002 - 2x128 13.5 MHZ periods, 18.96
s
0x003 - 3x128 13.5 MHZ periods, 28,44
s
....
0x3FF - 1023x128 13.5 MHz periods, 9.69 ms
....
0xFFF - 4095x128 13.5 MHz periods, 38.8 ms
Note: This eld in only valid in Event Timestamping mode
(FIFO_MOD E = 00 and EVENT_MODE != 00)
3:2
EVENT_MODE
R/W
0
Timestamping event mode:
00 - event detection disabled
01 - capture negative edge
10 - capture positive edge
11 - capture either edge
NOTE: This eld is valid in Event Timestamping mode
(FIFO_MODE[1:0]=00)
1:0
FIFO_MODE
R/W
0
This bit selects what mode of operation the FIFO queue is in:
00 - Event Timestamping (or Disabled if EVENT_MODE[1:0] = 00)
01 - Signal Sampling
10 - Pattern Generation using timestamps.
11 - Pattern Generation using samples.
Offset 0x10,4064 -> 0x070
IO_SELa<0-3>
31:24
IO_SEL_3
R/W
0
This eld selects a GPIO pin which should be merged with the
GPIO pin selected by IO_SEL_0, IO_SEL_1 and IO_SEL_2 to
enable 4-bit samples in one FIFO queue.
Note: This eld is only used in Signal Sampling mode and Pattern
Generation using samples mode and is enabled by EN_IO_SEL
23:16
IO_SEL_2
R/W
0
This eld selects a GPIO pin which should be merged with the
GPIO pins selected by IO_SEL_0, IO_SEL_1 and IO_SEL_3 to
enable 4-bit samples in one FIFO queue.
Note: This eld is only used in Signal Sampling mode and Pattern
Generation using samples mode and is enabled by EN_IO_SEL
15:8
IO_SEL_1
R/W
0
This eld selects a GPIO pin which should be merged with the
GPIO pin selected by IO_SEL_0 to enable 2-bit samples in one
FIFO queue.
Note: This eld is only used in Signal Sampling mode and Pattern
Generation using samples mode and is enabled by EN_IO_SEL
Table 10: Sampling and Pattern Generation Control Registers for the FIFO Queues
Bit
Symbol
Acces
s
Value
Description