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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 7: PCI-XIO Module
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
7-261
3
en_int_sig_serr
R/W
0
Enable interrupt on System Error Status
2
en_int_pci_r_mabort
R/W
0
Enable interrupt on PCI Received Master Abort Status
1
en_int_pci_r_tabort
R/W
0
Enable interrupt on PCI Received Target Abort Status
0
en_int_pci_s_tabort
R/W
0
Enable interrupt on PCI Signaled Target Abort Status
Offset 0x04 0FE8
PCI Interrupt Clear
31:27
Reserved
R
0
26
clr_pcii_wr_err
W
0
Clear PCI DTL initiator write error ag
25
clr_pcii_rd_err
W
0
Clear PCI DTL initiator read error ag
24
clr_xio_wr_err
W
0
Clear XIO DTL target write error ag
23
clr_xio_rd_err
W
0
Clear XIO DTL target read error ag
22
clr_pcir_wr_err
W
0
Clear mmio register DTL target write error ag
21
clr_pcir_rd_err
W
0
Clear mmio register DTL target read error
20
clr_pwrstate_chg
W
0
Clear power state change register ag
19
Reserved
R
0
18
clr_pci2_wr_err
W
0
Clear PCI2 DTL target write error ag
17
clr_pci2_rd_err
W
0
Clear PCI2 DTL target read error ag
16
clr_pci1_wr_err
W
0
Clear PCI1 DTL target write error ag
15
clr_pci1_rd_err
W
0
Clear PCI1 DTL target read error ag
14
clr_pci_xio_ack_done
W
0
Clear pci_xio_ack done ag
13:12
Reserved
R
0
11
clr_serr_seen
W
0
Clear serr_seen ag
10
Reserved
R
0
9
clr_pci_err
W
0
Clear pci_err ag
8
clr_base10_subword
W
0
Clear Subword Attempt to Base10 Error Status
7
clr_base14_subword
W
0
Clear Subword Attempt to Base14 Error Status
6
clr_base18_subword
W
0
Clear Subword Attempt to Base18 Error Status
5
clr_pci_mstr_parity_err
W
0
Clear PCI Master Parity Error
4
clr_pci_parity
W
0
Clear PCI Parity Error Status
3
clr_sig_serr
W
0
Clear System Error Status
2
clr_pci_r_mabort
W
0
Clear PCI Received Master Abort Status
1
clr_pci_r_tabort
W
0
Clear PCI Received Target Abort Status
0
clr_pci_s_tabort
W
0
Clear PCI Signaled Target Abort Status
Offset 0x04 0FEC
PCI Interrupt Set
31:27
Reserved
R
0
26
set_pcii_wr_err
W
0
Set PCI DTL initiator write error ag
25
set_pcii_rd_err
W
0
Set PCI DTL initiator read error ag
24
set_xio_wr_err
W
0
Set XIO DTL target write error ag
23
set_xio_rd_err
W
0
Set XIO DTL target read error ag
Table 8: Registers Description
Bit
Symbol
Acces
s
Value
Description