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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 26: Memory Arbiter
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
26-783
Offset 0x06 4200—423C Entries of Priority List (Set A)
Note: Offset 0x200 has the highest priority.
Offset 0x06 4280—42BC Entries of Round Robin List #1 (Set A)
Offset 0x06 4300—431C Entries of Round Robin List #2 (Set A)
Arbiter Registers (Set B)
Offset 0x06 4400—45FC Entries of TDMA Timing Wheel (Set B)
31:10
Reserved
R
0
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
9:8
R/W Grant
R/W
0
Grant on read, write or both.
0x0 = grant independent whether it is a read or write
0x1, 0x2, 0x3 = reserved
7:5
Reserved
R
0
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
4:0
Agent_ID
R/W
0
ID of the agent that is identied by this entry.
Offset 0x06 4600—463F Entries of Priority List (Set B)
Note: Offset 0x200 has the highest priority.
Offset 0x06 4680—46BC Entries of Round Robin List #1 (Set B)
Offset 0x06 4700—471C Entries of Round Robin List #2 (Set B)
Offset 0x06 4800
NR_ENTRIES_A (Set A)
31:28 Reserved
R/W
0
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
27:24 round_robin2_entries
R/W
0
Number of valid entries in last round robin list #2
Programming any value > 8 will result in use of the full round-robin
list.
23:21 Reserved
R/W
0
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
20:16 round_robin1_entries
R/W
0
Number of valid entries in rst round robin list #1
Programming any value > 16 will result in use of the full round-robin
list.
15:13 Reserved
R/W
0
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
12:8
priority_entries
R/W
0
Number of valid entries in priority list
Programming any value > 16 will result in use of full priority list.
7:0
TDMA_entries
R/W
0
Number of valid entries in TDMA wheel
Programming any value > 128 will result in use of all 128 entries.
Offset 0x06 4804
NR_ENTRIES_B (Set B)
Table 3: PMAN (Hub) Arbiter Registers …Continued
Bit
Symbol
Acces
s
Value
Description