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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
23-677
In QoS mode, that is, when the EnableQoS bit of the Command register is set, the
real-time transmit registers correspond to the registers of the low-priority transmit
channel and the non-real-time transmit registers correspond to the registers of the
high priority transmit channel.
3.2 Register Denitions
This section denes the bits of the individual LAN100 registers. The MII Interface
registers are mapped to addresses in the range 0x07 2000 – 0x07 20FC. For more
information about the MII Interface registers than is provided here, please refer to
[2].0x07 2230
PatternMatchMask0L
R/W
Bit 31:0 of Pattern Match 0
0x07 2234
PatternMatchMask0H
R/W
Bit 63:32 of Pattern Match 0
0x07 2238
PatternMatchCRC0
R/W
CRC Value for Pattern Match 0
0x07 223C
PatternMatchSkip0
R/W
Skip Bytes for Pattern Match 0
0x07 2240
PatternMatchMask1L
R/W
Bit 31:0 of Pattern Match 1
0x07 2244
PatternMatchMask1H
R/W
Bit 63:32 of Pattern Match 1
0x07 2248
PatternMatchCRC1
R/W
CRC Value for Pattern Match 1
0x07 224C
PatternMatchSkip1
R/W
Skip Bytes for Pattern Match 1
0x07 2250
PatternMatchMask2L
R/W
Bit 31:0 of Pattern Match 2
0x07 2254
PatternMatchMask2H
R/W
Bit 63:32 of Pattern Match 2
0x07 2258
PatternMatchCRC2
R/W
CRC Value for Pattern Match 2
0x07 225C
PatternMatchSkip2
R/W
Skip Bytes for Pattern Match 2
0x07 2260
PatternMatchMask3L
R/W
Bit 31:0 of Pattern Match 3
0x07 2264
PatternMatchMask3H
R/W
Bit 63:32 of Pattern Match 3
0x07 2268
PatternMatchCRC3
R/W
CRC Value for Pattern Match 3
0x07 226C
PatternMatchSkip3
R/W
Skip Bytes for Pattern Match 3
0x07 2270
to
0x07 2FDC
Reserved
Standard Registers
0x07 2FE0
IntStatus
RO
Interrupt Status register
0x07 2FE4
IntEnable
R/W
Interrupt Enable register
0x07 2FE8
IntClear
WO
Interrupt Clear register
0x07 2FEC
IntSet
WO
Interrupt Set register
0x07 2FF0
Reserved
0x07 2FF4
PowerDown
R/W
Power-down register
0x07 2FF8
Reserved
0x07 2FFC
ModuleID
RO
Module ID
Table 1: LAN100 MMIO Register Map
Offset
Name
R/W
Function