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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 8: General Purpose Input Output Pins
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
8-287
4.
MMIO Registers
Table 6: Register Summary
Name
Description
0x10,4000
Mode Control 0
The Mode Control bit pairs which control GPIO pins 15-0.
0x10,4004
Mode Control 1
The Mode Control bit pairs which control GPIO pins 31-16.
0x10,4008
Mode Control 2
The Mode Control bit pairs which control GPIO pins 47-32.
0x10,400C
Mode Control 3
The Mode Control bit pairs which control GPIO pins 60-48.
0x10,4010
MASK and IO Data 0
MASK and IO data for GPIO pins 15-0.
0x10,4014
MASK and IO Data 1
MASK and IO data for GPIO pins 31-16.
0x10,4018
MASK and IO Data 2
MASK and IO data for GPIO pins 47-32.
0x10,401C
MASK and IO Data 3
MASK and IO data for GPIO pins 60-48.
0x10,4020
Internal Signals
Internal signals to be timestamped, software readable.
0x10,4024
GPIO_EV0
GPIO signal monitoring OR pattern generation control register for FIFO queue 0.
0x10,4028
GPIO_EV1
GPIO signal monitoring OR pattern generation control register for FIFO queue 1.
0x10,402C
GPIO_EV2
GPIO signal monitoring OR pattern generation control register for FIFO queue 2.
0x10,4030
GPIO_EV3
GPIO signal monitoring OR pattern generation control register for FIFO queue 3.
0x10,4034
GPIO_EV4
GPIO signal monitoring control register for timestamp unit 0
0x10,4038
GPIO_EV5
GPIO signal monitoring control register for timestamp unit 1
0x10,403C
GPIO_EV6
GPIO signal monitoring control register for timestamp unit 2
0x10,4040
GPIO_EV7
GPIO signal monitoring control register for timestamp unit 3
0x10,4044
GPIO_EV8
GPIO signal monitoring control register for timestamp unit 4
0x10,4048
GPIO_EV9
GPIO signal monitoring control register for timestamp unit 5
0x10,404C
GPIO_EV10
GPIO signal monitoring control register for timestamp unit 6
0x10,4050
GPIO_EV11
GPIO signal monitoring control register for timestamp unit 7
0x10,4054
GPIO_EV12
GPIO signal monitoring control register for timestamp unit 8
0x10,4058
GPIO_EV13
GPIO signal monitoring control register for timestamp unit 9
0x10,405C
GPIO_EV14
GPIO signal monitoring control register for timestamp unit 10
0x10,4060
GPIO_EV15
GPIO signal monitoring control register for timestamp unit 11
0x10,4064
IO_SEL0
IO Select register for FIFO queue 0
0x10,4068
IO_SEL1
IO Select register for FIFO queue 1
0x10,406C
IO_SEL2
IO Select register for FIFO queue 2
0x10,4070
IO_SEL3
IO Select register for FIFO queue 3
0x10,4074
PG_BUF_CTRL0
Pattern Generation DMA buffer control register. for FIFO queue 0
0x10,4078
PG_BUF_CTRL1
Pattern Generation DMA buffer control register. for FIFO queue 1
0x10,407C
PG_BUF_CTRL2
Pattern Generation DMA buffer control register for FIFO queue 2.
0x10,4080
PG_BUF_CTRL3
Pattern Generation DMA buffer control register for FIFO queue 3.
0x10,4084
BASE1_PTR0
Base address for DMA buffer 1 of FIFO queue 0.
0x10,4088
BASE1_PTR1
Base address for DMA buffer 1 of FIFO queue 1.
0x10,408C
BASE1_PTR2
Base address for DMA buffer 1 of FIFO queue 2.