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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 29: Endian Mode
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
29-810
6.
Implementation Details
The PNX15xx/952x Series system has two different bus structures:
Device Control and Status Network, or DCS Network; and
Pipelined Memory Access Network, or PMAN Network, or MTL bus.
6.1 PMAN Network Endian Block Diagram
The system endian mode of operation is designated to each component by the
system big-endian signal - ’1’ for big-endian mode, ’0’ for little-endian mode.
Referring to
Figure 1, note that both modules are identical. They perform all DMA
data transfers across a standard 32-bit “DTL interface.” Module 1 uses the data
ordering rules according to
Table 5 while Module 2 uses the address invariance rules
according to
Table 6. The PMAN interface to Module 1 therefore has to convert the
data format to address invariant format (this is done in the "Endian Swap" portion of
the PMAN structure) while Module 2 does not require any such conversion (the
module is already in the address invariant format). The rest of the PMAN and
memory interface structure is address invariant.
The PMAN Endian Swap unit (as shown for Module 1) or the Module endian swap
unit (as shown in Module 2), must deal with unit endian swapping and unit packing
.
Swapping is dened as “positioning each byte of a unit correctly with respect to the
memory byte address that it is supposed to go to.” Swapping is what implements the
CPU rule. Packing is dened as “the action that places consecutive units
simultaneously on a wider bus in order to implement the DMA rule.”
The DMA module need not be aware of the details of either the DTL, or the MTL Bus.
It just swaps and packs, based on its knowledge of unit size and system endian
mode, and creates the valid DTL interface data.
Figure 6:
Audio In Control/Status MMIO Registers
AI_STATUS (r/w)
AI_CTL (r/w)
BUF1_ACTIVE
OVERRUN
HBE (Highway bandwidth error)
BUF2_FULL
BUF1_FULL
RESERVED
RESET
CAP_ENABLE
CAP_MODE
SIGN_CONVERT
DIAG_MODE
OVR_INTEN
HBE_INTEN
BUF2_INTEN
BUF1_INTEN
ACK_OVR
ACK_HBE
ACK2
ACK1
31
27
23
19
15
11
7
3
0
31
27
23
19
15
11
7
0