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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 9: DDR Controller
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
9-341
Offset 0x06 5120
DDR_TRFC
31:4
Unused
R
-
These bits should be ignored when read, and written as 0’s.
3:0
TRFC
R/W
0xf
Auto refresh command period.
Offset 0x06 5124
DDR_TMRD
31:4
Unused
R
-
These bits should be ignored when read, and written as 0’s.
3:0
TMRD
R/W
2
Load mode register command cycle time.
Offset 0x06 5128
DDR_TCAS
31:4
Unused
R
-
These bits should be ignored when read, and written as 0s.
3:0
TCAS
R/W
8
CAS read latency, specied in halve cycles. I.e., a value of 0b0111
(7) represents a CAS delay of 3.5 cycles (7 halve cycles).
Offset 0x06 512C
DDR_RF_PERIOD
31:6
Unused
R
-
These bits should be ignored when read, and written as 0s.
15:0
RF_PERIOD
R/W
3515
Refresh period expressed in terms of cycles. Typically a refresh is
required at an average interval of 15.625 us. For a 100 MHz. device
this translates into a RF_PERIOD value of 1562. For a 200 MHz.
device this translates into a RF_PERIOD value of 3125.
Arbitration Parameters
Offset 0x06 5180
ARB_CTL
31
CPU_DMA_DECR
R/W
1
‘0’: Do not decrement CPU counters when in a DMA_WINDOW.
‘1’: Do decrement CPU counters when in a DMA_WINDOW.
30
CPU_HRT_SRT_ENAB
LE
R/W
0
‘0’: Controller will interpret that DMA port contains only Hard Real
Time DMA requests.
‘1’: Controller will interpret that DMA port contains Hard Real Time
or Soft Real Time DMA requests.
29
BLB_ENABLE
R/W
0
‘0’: Disable Back Log Buffer
‘1’: Enable Back Log Buffer.
28
DYN_RATIOS
R/W
0
‘0’: Use Static Ratios. This means accounts are incremented by the
value (RATIO+ DDR burst size (in terms of cycles)) whenever a
CPU DDR burst is performed.
‘1’: Enable Dynamic Ratios. This means accounts are incremented
by the value RATIO every clock cycle that is spent on servicing a
CPU DDR burst. This feature also causes account not to decrement
during clock cycles that are spent on CPU DDR bursts.
27:18
Reserved
R
-
These bits should be ignored when read, and written as 0s.
Table 9: Register Description
Bit
Symbol
Access
Value
Description