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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
23-738
After a reset, the FSM is in the INACTIVE state. As soon as the RxEnable bit is set in
the Command register, the FSM transitions to the ACTIVE state. As soon as the
RxEnable bit is cleared, the FSM returns to the INACTIVE state. If the Receive
Datapath is busy receiving a packet when it is put in the disabled state, packet
reception will continue and the packet will be received completely and stored to
memory along with its status before it returns to the INACTIVE state.
is inactive until the datapath is re-enabled.
5.14.2
Enabling and Disabling Transmission
After reset, the transmit function of the LAN100 is disabled. The Transmit Datapaths
(Tx and TxRt) must be enabled separately. The device driver enables the Tx datapath
by setting the TxEnable bit in the Command register to 1. The device driver enables
the TxRt datapath by setting the TxRt bit in the Command register to 1.
The status of the Transmit Datapaths can be monitored by the device driver by
reading the TxStatus and TxRtStatus bits of the Status register. The FSM for both Tx
After reset, the FSMs are in the INACTIVE state. As soon as the Tx(Rt)Enable bit is
set in the Command register and the Produce and Consume indices are not equal,
the FSM transitions to the ACTIVE state. As soon as the Tx(Rt)Enable bit is cleared
and the Transmit Datapath has completed all pending transmissions including
committing the transmission status to memory, the FSM returns to the INACTIVE
state. The FSM will also return to the INACTIVE state if the Produce and Consume
indices are equal again, that is, when all packets have been transmitted.
As shown in
Figure 15, the Transmit Datapath is inactive after a soft reset (see
5.15 Transmission Padding and CRC
In the event that a packet is received with a length of less than 60 bytes (or 64 bytes
for VLAN frames) the LAN100 can pad the packet to 64 or 68 bytes, including a
4-byte CRC Frame Check Sequence (FCS). Padding is affected by the value of the
Figure 15: Transmit Active/Inactive state machine
ACTIVE
RxStatus=1
INACTIVE
RxStatus=0
Reset
TxEnable &&
TxProduceIndex != TxConsumeIndex
(!TxEnable && not busy transmitting) ||
TxProduceIndex == TxConsumeIndex