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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 2: Overview
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
2-93
Software (on the TM3260 CPU) can be written endian-mode independent, even
when doing SIMD style vectorized computations
Remark: The native formats of PNX15xx/952x Series include the most common
indexed, packed RGB, packed YUV and planar YUV formats used by Microsoft
DirectX and Apple Quicktime, with 100% bit layout compatibility in little and big-endian
modes of operation, respectively.
Remark: TM3260 software image processing stages and encoders/decoders
typically use semi-planar or planar 4:2:0 or 4:2:2 formats as input and output.
1. VIP output of RGB is mutually exclusive with horizontal scaling
2. Shown are the 2D engine frame buffer formats where drawing, RasterOps and
alpha-blending of surfaces can be accelerated. Additionally, the 2D Drawing
Engine host port supports 1 bpp monochrome font/pattern data, and 4 and 8-bit
alpha only data for host-initiated anti-aliased drawing.
7.2 Video Input Processor
The Video Input Processor (VIP) handles incoming digital video and processes it for
use by other components of the PNX15xx/952x Series. VIP provides 10-bit accurate
processing. The VIP provides the following functions:
Receives 10-bit YUV4:2:2 like digital video format from the video port. The data is
dithered down to in-memory 8-bit data format. The YUV4:2:2 data stream
typically comes from devices such as the SAA 711x, which digitize PAL or NTSC
analog video. The input data can be other than YUV, like YCrCb as long as it
follows the YUV 4:2:2 video format.
Table 5: Native Pixel Format Summary
Name
Note
VIP
out
MBS
in
MBS
out
2D
engine
(2)
QVCP-
LCD
in
1 bpp indexed
CLUT entry = 24-bit color + 8-bit alpha
x
2 bpp indexed
xx
4 bpp indexed
xx
8 bpp indexed
xx
x
RGBa 4444
16-bit unit, containing one pixel with alpha
(1)
x
RGBa 4534
(1)
x
RGB 565
16-bit unit, containing one pixel, no alpha
(1)
x
RGBa 8888
32-bit unit, containing one pixel with alpha
(1)
x
packed YUVa 4:4:4
32-bit unit containing one pixel with alpha
x
packed YUV 4:2:2 (UYVY)
16-bit unit, two successive units contain two
horizontally adjacent pixels, no alpha
xx
x
packed YUV 4:2:2 (YUY2, 2vuy)
x
planar YUV 4:2:2
three arrays, one for each component
x
semi-planar YUV 4:2:2
two arrays, one with all Ys, one with U and Vs
x
planar YUV 4:2:0
three arrays, one for each component
x
semi-planar YUV 4:2:0
two arrays, one with all Ys, one with U and Vs
x