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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 15: Audio Output
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
15-515
2.6.1
Serial Frame Limitations
Due to the implementation, there is a minimum serial frame length requirement that is
operating-mode dependent according to
Table 4.2.6.2
WS Characteristics
The WS signal is used to dene the start point of a serial frame. The start of a frame
can be marked by a transition on WS 1 clock before the start of the rst bit of a new
frame. This WS transition can be programmed to be either a positive or a negative
edge transition.
In addition, the WS signal can be programmed to be a 50% duty cycle wave form or a
pulse that is 1 clock cycle wide. If the WS is congured to be 1 single clock wide
pulse, the pulse spans the 2 clock cycles preceding the rst bit of the new frame. If
the WS is congured to be a 50% duty cycle waveform, the active edge of the WS
signal occurs 1 clock cycle before the rst bit of the new frame. If the serial frame is of
an even bit count, then the second transition of the WS signal occurs in the clock
cycle before the halfway point of the serial frame. If the serial frame is of an odd bit
count, then the portion of the WS wave that is in the low state has the extra clock
cycle.
With an odd bit count for a serial frame and with a frame starting with a negative edge
of the WS, a 50% duty cycle WS signal would have the rst part of the WS signal 1
clock longer than the second half. With a positive edge of the WS signal marking the
start of a serial frame, the second half of the serial frame would have a WS signal
longer by 1 clock cycle.
2.6.3
I2S Serial Framing Example
Figure 4 and
Table 5 show how the Audio Out module MMIO registers should be set
to transmit 16 or 32 bits of stereo data via an I2S serial standard to an 18-bit D/A
converter with a 64-bit serial frame.
Table 4: Minimum Serial Frame Length in Bits
Operating Mode
Minimum Serial Frame Length
16 bit/sample, mono
13 bits
32 bit/sample, mono
13 bits
16 bit/sample, stereo
13 bits
32 bit/sample, stereo
36 bits
Figure 4:
Serial Frame (64 Bits) of a 18-Bit Precision I2S D/A Converter
52
SCK
WS
SDx
left channel data n (18)
right channel datan(18)
left channel datan+1(18)
12
3
17 18
30 31 32
33
49 50 51
62 63
0
1
0