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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 15: Audio Output
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
15-516
Remark: The transfer of data from SDRAM into the Audio Out module's transmit
FIFOs is initiated by the transition of WS, not by transmit enable. As a consequence,
there is a delay between the receipt of the first WS pulse and the transmission of the
first data. The length of this delay is dependent on system load and is not easily
predictable.
2.7 Codec Control
In addition to the left and right data elds that are generated based on autonomous
DMA action, a serial frame generated by Audio Out can be set to contain one or two
control elds of up to 16 bits in length. Each control eld can be independently
enabled or disabled by the CC1_EN, CC2_EN bits in AO_CTL.
The content shifted into the frame is taken from the CC1 and CC2 eld in the AO_CC
register. The CC1_POS and CC2_POS elds in the AO_CFC register determine the
rst bit position in the frame where the control eld is emitted observing the setting of
DATAMODE (i.e., LSB or MSB rst).
The CC_BUSY bit in AO_STATUS indicates if the Audio Out unit is ready to receive
another CC1, CC2 value pair. Writing a new value pair to AO_CC writes the value into
As soon as both CC1 and CC2 values have been copied to a shadow register in
preparation for transmission, CC_BUSY is negated, indicating that the Audio Out
logic is ready to accept a new codec control pair. The old CC1/CC2 data is
transmitted continuously (i.e., software is not required to provide new CC1 and CC2
data).
Software must ensure that the CC_BUSY status is negated before writing a new
CC1, CC2 pair. The user, by the process of waiting on CC_BUSY, can reliably emit a
sequence of individual audio frames with distinct control eld values. This can, for
example, be used during codec initialization. Note that no provision is made for
interrupt-driven operation of such a sequence of control values. It is assumed, after
initialization, that the value of control elds determines slowly changing,
asynchronous parameters such as output volume.
Table 5: Example Setup For 64-Bit I2S Framing
Field
Value Explanation
POLARITY
0
Frame starts with negative edge Audio Out WS.
LEFTPOS
0
LEFT[MSB] will go to serial frame position 0.
RIGHTPOS
32
RIGHT[MSB] will go to serial frame position 32.
DATAMODE
0
MSB rst.
SSPOS
0
Stop with LEFT/RIGHT[0], send 0s after.
(For 32-bit/sample mode, this eld could be set to 14 to ensure
zeroes in all unused bit positions.)
CLOCK_EDGE
0
Audio Out SD change on negative edge Audio Out SCK
WSDIV
63
Serial frame length = 64
WS_PULSE
0
Emit 50% duty cycle Audio Out WS.