
NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 18: SPDIF Input
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
18-576
Offset 0x10 A034
SPDI_UBITS2
31:0
UBITS [31:0]
R
0
User bit 2 contains the state of user bytes 4, 5, 6 and 7 of the block
according to SPDI_CTL.UCBITS_SEL. The SPDI_UBITS register
will always reect the condition of the current decoded block of 192
frames. Register bit meaning will depend upon the source
transmission.
Offset 0x10 A038
SPDI_UBITS3
31:0
UBITS [31:0]
R
0
User bit 3 contains the state of user bytes 8, 9, 10 and 11 of the
block according to SPDI_CTL.UCBITS_SEL. The SPDI_UBITS
register will always reect the condition of the current decoded block
of 192 frames. Register bit meaning will depend upon the source
transmission.
Offset 0x10 A03C
SPDI_UBITS4
31:0
UBITS [31:0]
R
0
User bit 4 contains the state of user bytes 12, 13, 14 and 15 of the
block according to SPDI_CTL.UCBITS_SEL. The SPDI_UBITS
register will always reect the condition of the current decoded block
of 192 frames. Register bit meaning will depend upon the source
transmission.
Offset 0x10 A040
SPDI_UBITS5
31:0
UBITS [31:0]
R
0
User bit 5 contains the state of user bytes 16, 17, 18 and 19 of the
block according to SPDI_CTL.UCBITS_SEL. The SPDI_UBITS
register will always reect the condition of the current decoded block
of 192 frames. Register bit meaning will depend upon the source
transmission.
Offset 0x10 A044
SPDI_UBITS6
31:0
UBITS [191:159]
R
0
User bit 6 contains the state of user bytes 20, 21, 22 and 23 of the
block according to SPDI_CTL.UCBITS_SEL. The SPDI_UBITS
register will always reect the condition of the current decoded block
of 192 frames. Register bit meaning will depend upon the source
transmission.
Offset 0x10 A048—AFDC Reserved
Offset 0x10 AFE0
SPDI_STATUS
31:10
Unused
-
9
UNLOCK
R
0
UNLOCK active. This ag gets set to logic ‘1’ if the SPDIF Input
receiver is NOT locked onto an incoming stream. Programmers can
use this UNLOCK indication, in conjunction with the LOCK bit, to
determine the state of the receiver or to make a decision to adjust
the oversampling frequency. See the denition of the LOCK bit.
Possible causes of an out-of-lock state are:
i) The oversampling frequency is too high or too low with respect
to the applied input SPDIF sample rate.
ii) Too much jitter in SPDIF input stream.
iii) Absent, invalid or corrupted SPDIF stream applied to the
interface/receiver.
The ag can be cleared by a software write to UNLOCK_CLR.
8
UCBITS
R
0
User/Channel bits available. This ag is set if a new set of user data
bits and channel status bits have been written to the SPDI_UBITSx
and SPDI_CBITSx registers. Updated on a block basis.
Table 6: SPDIF Input Registers …Continued
Bit
Symbol
Acces
s
Value
Description