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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 7: PCI-XIO Module
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
7-263
30
Signaled System Error
R/W
0
This bit is set whenever the device asserts SERR. Write 1 to clear.
29
Received Master Abort
R/W
0
Set by the PCI master when its transaction is terminated with a
master abort. Write 1 to clear.
28
Received Target Abort
R/W
0
Set by the PCI master when its transaction is terminated with a
target abort. Write 1 to clear.
27
Signaled Target Abort
R/W
0
Set by the PCI target when it terminates a transaction with a target
abort. Write 1 to clear.
26:25
Devsel Timing
R
01
The PCI target uses medium DEVSEL timing.
24
Master Data Parity Error R/W
0
Set by the PCI master when PERR is observed.
23
Fast Back-to-Back
Capable
R
1
The PCI supports fast back-to-back transactions.
22
Reserved
R
0
21
66 MHz Capable
R
cfg*
0 = 33 MHz PCI (The PNX15xx/952x Series is 33 MHz).
*Value determined by pci_setup register.
20
Capabilities List
R
1
Indicates a new Capabilities linked list is available at offset 40h.
19:10
Reserved
R
0000
9
Fast back-to-back
enable
R/W
0
Enable fast back-to-back transactions for PCI master.
8
SERR enable
R/W
0
Enable SERR to report system errors.
7
Stepping Control
R
0
Address stepping is not supported.
6
Parity Error Response
R/W
0
0 = No parity error response
1 = Enable parity error response.
5
VGA Palette Snoop
R
0
VGA is not supported.
4
Memory Write &
Invalidate
R/W
0
Enable use of memory write and invalidate.
3
Special Cycles
R
0
Special cycles are not supported.
2
Enable Bus Master
R/W
0
Enable the PCI bus master.
1
Enable Memory space
R/W
0
Enable all memory apertures.
0
IO Space
R
0
The PCI module does not respond to IO transactions.
Offset 0x0008
Class Code/Revision ID
31:8
Class Code
R/W*
048000
The PNX15xx/952x Series is dened as a multimedia device.
*The boot loader may change the class code to an alternate value if
done before writing to the pci_setup register.
7:0
Revision ID
R
1
Revision ID. Will initially be assigned to 0. Revision ID must not be
synthesized. It will need to be changed with revised silicon, whether
for bug xes or enhancements.
Offset 0x000C
Latency Timer/Cache Line Size
31:16
Reserved
R
0x0000
Note: BIST is not implemented. Header is 0.
15:8
Latency Timer
R/W
0
Latency Timer
7:0
Cache Line Size
R/W
0
Cache Line Size
Offset 0x0010
Base10 Address Register
Table 9: PCI Conguration Registers
Bit
Symbol
Acces
s
Value
Description