
NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 17: SPDIF Output
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
17-552
If the software fails to provide a new buffer of data in time, and both DMA buffers
empty out, the SPDO hardware raises the UNDERRUN ag in SPDO_STATUS.
Transmission switches over to the use of the next buffer, but the data transmitted is
from the previously transmitted buffer. IF UDR_INTEN is asserted, an interrupt will be
generated. The UNDERRUN ag is sticky - it will remain asserted until the software
clears it by writing a ‘1’ to ACK_UDR.
A lower level error can also occur when the limited size internal buffer empties out
before it can be relled across the data bus. This situation can arise only if insufcient
bandwidth is allocated to SPDO from the bus arbiter. In this case, the Highway
Bandwidth Error (HBE) error ag is raised.
3.4.2
HBE and Latency
If the arbiter is set up with an insufcient latency guarantee, a situation can arise that
requested data will not arrive in time, (when a new output sample is due). In that case
the HBE error is raised, and the last sample for each channel will be repeated until
the new buffer is refreshed. The HBE condition is sticky, and can only be cleared by
an explicit ACK_HBE. This condition indicates an incorrect setting of the arbiter.
The arbiter needs to guarantee that the maximum latency required by the SPDO
block can always be met.
Given an output data rate
fs in samples/sec, 2 x 32 bits are required each sample
interval. The arbiter should be set to have a latency so that the buffer is relled before
a sample interval expires. Refer to
Table 3 for example latency requirements.
3.4.3
Interrupts
The SPDO block generates an interrupt if one of the following status bit ags, and its
corresponding INTEN ag are set: BUF1_EMPTY, BUF2_EMPTY, HBE,
All these status ags are ‘sticky’, i.e. they are asserted by hardware when a certain
condition occurs, and remain set until the interrupt handler explicitly clears them by
writing a ‘1’ to the corresponding ACK bit in SPDO_CTL. The SPDO hardware takes
the ag away in the clock cycle after the ACK is received. This allows immediate
return from interrupt once performing an ACK.
3.4.4
Timestamp Events
SPDO exports event signals associated with audio transmission to the central
timestamp/timer function on-chip. The central timestamp/timer function can be used
to count the number of occurrences of each event or timestamp the occurrence of the
event or both. The event will be a positive edge pulse with the duration of the event to
be greater than or equal to 200 ns. The specic event exported is as follows:
Table 3: SPDO Block Latency Requirements
fs (kHz)
1/fs (nSec)
Max. latency (9/fs) (uSec)
32.000
31250
281
44.100
22675
204
48.000
20833
187
96.000
10416
94