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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 11: QVCP
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
11-409
12:0
LayerNStartY
R/W
0
Layer N Start y position (from zero at top) in lines. Negative Y
position is allowed.
Note: In interlaced modes the following rules apply:
Fine=0 : LayerNStartY is always relative to frame position i.e.,
LayerNStartY=100 will display the layer at STG_Y_POS=100
position.
Fine=1 : LayerNStartY is always relative to eld position i.e.,
LayerNStartY=100 will be translated to display layer at
STG_Y_POS=100/2=50 position.
Fine=1 is recommanded in interlaced mode.
Fine=0 is recommanded in progressive mode.
Whenever layer y position is changed, please make sure other y
position sensitive register settings are still satised, such as :
start fetch register 10E2C8,
shadow reload position 10E1F0
layer start eld register 10E23C (for interlaced mode)
Offset 0x10 E234
Layer Size
31:28
Unused
-
27:16
LayerNHeight
R/W
0
Layer N height in lines.
15:12
Unused
-
11:0
LayerNWidth
R/W
0
initial (before scaling) Layer N width, in pixels.
Offset 0x10 E238
Pedestal and O/P format
31:24
Pedestal_up
R/W
0
Pedestal to be added to Upper input
(pedestal_up is a 2’s complement number from -128 to 127)
The pedestal removal is performed after the color key unit, before
dithering.
23:16
Pedestal_mid
R/W
0
Pedestal to be added to Middle input
(pedestal_mid is a 2’s complement number from -128 to 127)
The pedestal removal is performed after the color key unit, before
dithering
15:8
Pedestal_low
R/W
0
Pedestal to be added to Lower input
(pedestal_low is a 2’s complement number from -128 to 127)
The pedestal removal is performed after the color key unit, before
dithering
7:3
Unused
-
2:1
OP_format
R/W
0
Output type selector
0 = data expansion from 8 to 9 bit through multiply by two (zero in
LSB)
1 = data expansion from 8 to 9 bit through multiply by two (MSB
in LSB position)
2,3 = data expansion from 8 to 9 bit through multiply by two
(undither operation)
0
FRMT_4xx
R/W
0
Input format indicator
0 = Input is in 4:4:4 format
1 = Input is in 4:2:2 format
Offset 0x10 E23C
Layer Pixel Processing
Table 20: QVCP 1 Registers …Continued
Bit
Symbol
Acces
s
Value
Description