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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 5: The Clock Module
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
5-193
0
en_clk_qvcp_pix
R/W
1
1: enable clk_qvcp_pix
Offset 0x04,7208
CLK_QVCP_PROC_CTL
31:8
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
7
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
6:3
sel_clk_qvcp_proc_src
R/W
0111
0000: clk_qvcp_proc_src = clk_144
0001: clk_qvcp_proc_src = clk_133
0010: clk_qvcp_proc_src = clk_108
0011: clk_qvcp_proc_src = clk_96
0100: clk_qvcp_proc_src = clk_86
0101: clk_qvcp_proc_src = clk_78
0110: clk_qvcp_proc_src = clk_58
0111: clk_qvcp_proc_src = clk_39
1000: clk_qvcp_proc_src = clk_33
1001: clk_qvcp_proc_src = clk_17
Maximum speed supported is 96 MHz.
Other higher speeds are reserved for future use.
2:1
sel_clk_dtl_mmio
R/W
00
00: clk_qvcp_proc = 27 MHz xtal_clk
01: clk_qvcp_proc = clk_qvcp_proc_src
10: clk_qvcp_proc = 27 MHz xtal_clk
11: clk_qvcp_proc = XIO_D[9]
0
en_clk_proc
R/W
1
1: enable clk_qvcp_proc
Offset 0x04,720C
CLK_LCD_TIMESTAMP_CTL
31:4
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
3
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
2:1
sel_clk_lcd_timestamp
R/W
00
00: clk_lcd_timestamp = 27 MHz xtal_clk
01: clk_lcd_timestamp = 27 MHz xtal_clk
10: clk_lcd_timestamp = 27 MHz xtal_clk
11: clk_lcd_timestamp = XIO_D[10]
0
en_clk_lcd_timestamp
R/W
1
1: enable clk_lcd_timestamp
Offset 0x04,7210
CLK_VIP_CTL
31:5
Reserved
R/W
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
4
turn_off_ack
R
0
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
Table 11: CLOCK MODULE REGISTERS …Continued
Bit
Symbol
Acces
s
Value
Description