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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 17: SPDIF Output
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
17-555
29:27
TRANS_MODE
R/W
000
Transmission mode.
000 =IEC-60958 mode. Hardware performs bi-phase mark
encoding, preamble and parity generation, and transmits one
IEC-60958 subframe for each data descriptor word.
010 =Transparent mode, LSB rst. The 32 bit data descriptor
words are transmitted as is, LSB rst.
011 =Transparent mode, MSB rst. The 32 bit data descriptor
words are transmitted as is, MSB rst.
Other codes are reserved for future extensions.
Note: The transmission mode should only be changed while
transmission is disabled.
26:8
Reserved
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
7
UDR_INTEN
R/W
0
If UDR_INTEN = 1 and UNDERRUN = 1, an interrupt is asserted to
the chip level interrupt controller.
6
HBE_INTEN
R/W
0
If HBE_INTEN = 1 and HBE = 1, an interrupt is asserted to the chip
level interrupt controller.
5
BUF2_INTEN
R/W
0
If BUF2_INTEN = 1 and BUF2_EMPTY = 1, an interrupt is asserted
to the chip level interrupt controller.
4
BUF1_INTEN
R/W
0
If BUF1_INTEN = 1 and BUF1_EMPTY = 1, an interrupt is asserted
to the chip level interrupt controller.
3
ACK_UDR
W
0
1= Clear UNDERRUN.
0=No effect. Always reads as 0.
2
ACK_HBE
W
0
1= Clear HBE.
0= No effect.Always reads as 0.
1
ACK_BUF2
W
0
1= Clear BUF2_EMPTY. Informs SPDO that DMA buffer 2 is full.
0= No effect. Always reads as ‘0’.
SPDO_BASE2 is then used to fetch buffer1 data from memory.
0
ACK_BUF1
W
0
1= Clear BUF1_EMPTY. Informs SPDO that DMA buffer 1 is
0= No effect. Always reads as 0.
SPDO_BASE1 is then used to fetch buffer1 data from memory.
Offset 0x10 9008
Reserved
31:0
Reserved
-
R/W
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Offset 0x10 900C
SPDO_BASE1
31:6
SPDO_BASE1
0x0
R/W
Contains the memory address of DMA buffer 1.
If changed it must be set before ACK_BUF1.
5:0
Reserved
-
R
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Offset 0x10 9010
SPDO_BASE2
31:6
SPDO_BASE2
0x0-
R/W
Contains the memory address of DMA buffer 2.
If changed it must be set before ACK_BUF2.
5:0
Reserved
-
R
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Offset 0x10 9014
SPDO_SIZE
Table 6: SPDO Registers …Continued
Bit
Symbol
Acces
s
Value
Description