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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 8: General Purpose Input Output Pins
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
8-307
21
INT_OE_9_CLR
W
0
Active high clear for internal overrun interrupt for TSU 9.
20
INT_OE_8_CLR
W
0
Active high clear for internal overrun interrupt for TSU 8.
19
INT_OE_7_CLR
W
0
Active high clear for internal overrun interrupt for TSU 7.
18
INT_OE_6_CLR
W
0
Active high clear for internal overrun interrupt for TSU 6.
17
INT_OE_5_CLR
W
0
Active high clear for internal overrun interrupt for TSU 5.
16
INT_OE_4_CLR
W
0
Active high clear for internal overrun interrupt for TSU 4.
15
INT_OE_3_CLR
W
0
Active high clear for internal overrun interrupt for TSU 3.
14
INT_OE_2_CLR
W
0
Active high clear for internal overrun interrupt for TSU 2.
13
INT_OE_1_CLR
W
0
Active high clear for internal overrun interrupt for TSU 1.
12
INT_OE_0_CLR
W
0
Active high clear for internal overrun interrupt for TSU 0.
11
DATA_VALID_11_CLR
W
0
Active high clear for data valid interrupt for TSU 11.
10
DATA_VALID_10_CLR
W
0
Active high clear for data valid interrupt for TSU 10.
9
DATA_VALID_9_CLR
W
0
Active high clear for data valid interrupt for TSU 9.
8
DATA_VALID_8_CLR
W
0
Active high clear for data valid interrupt for TSU 8.
7
DATA_VALID_7_CLR
W
0
Active high clear for data valid interrupt for TSU 7.
6
DATA_VALID_6_CLR
W
0
Active high clear for data valid interrupt for TSU 6.
5
DATA_VALID_5_CLR
W
0
Active high clear for data valid interrupt for TSU 5.
4
DATA_VALID_4_CLR
W
0
Active high clear for data valid interrupt for TSU 4.
3
DATA_VALID_3_CLR
W
0
Active high clear for data valid interrupt for TSU 3.
2
DATA_VALID_2_CLR
W
0
Active high clear for data valid interrupt for TSU 2.
1
DATA_VALID_1_CLR
W
0
Active high clear for data valid interrupt for TSU 1.
0
DATA_VALID_0_CLR
W
0
Active high clear for data valid interrupt for TSU 0.
Offset 0x10,4FEC
INT_SET4
31:24
Unused
-
23
INT_OE_11_SET
W
0
Active high set for internal overrun interrupt for TSU 11.
22
INT_OE_10_SET
W
0
Active high set for internal overrun interrupt for TSU 10.
21
INT_OE_9_SET
W
0
Active high set for internal overrun interrupt for TSU 9.
20
INT_OE_8_SET
W
0
Active high set for internal overrun interrupt for TSU 8.
19
INT_OE_7_SET
W
0
Active high set for internal overrun interrupt for TSU 7.
18
INT_OE_6_SET
W
0
Active high set for internal overrun interrupt for TSU 6.
17
INT_OE_5_SET
W
0
Active high set for internal overrun interrupt for TSU 5.
16
INT_OE_4_SET
W
0
Active high set for internal overrun interrupt for TSU 4.
15
INT_OE_3_SET
W
0
Active high set for internal overrun interrupt for TSU 3.
14
INT_OE_2_SET
W
0
Active high set for internal overrun interrupt for TSU 2.
13
INT_OE_1_SET
W
0
Active high set for internal overrun interrupt for TSU 1.
12
INT_OE_0_SET
W
0
Active high set for internal overrun interrupt for TSU 0.
11
DATA_VALID_11_SET
W
0
Active high set for data valid interrupt for TSU 11.
10
DATA_VALID_10_SET
W
0
Active high set for data valid interrupt for TSU 10.
Table 18: GPIO Module Status Register for all 12 Timestamp Units
Bit
Symbol
Acces
s
Value
Description