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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
23-731
In half-duplex mode, when the TxFlowControl bit goes high, continuous preamble is
sent until TxFlowControl is deasserted. If the medium is idle, the LAN100 begins
transmitting its preamble, which raises carrier sense, causing all other stations to
defer. In the event that transmitting the preamble causes a collision, the back
pressure “rides through” the collision. The colliding station backs off, and then defers
to the back pressure. During back pressure, if the user wishes to send a frame, the
back pressure is interrupted, the frame is sent, and then the back pressure is
resumed. If TxFlowControl is asserted for longer than 3.3 ms in 10 Mbps mode or
0.33 ms in 100 Mbps mode, back pressure will cease sending preamble for several
byte times to avoid the jabber limit.
5.12 Receive ltering
5.12.1
Overview
The Ethernet module can lter out receive packets, analyzing the Ethernet
destination address in the packet. This capability greatly reduces the load on the host
system, because the many Ethernet packets that are typically addressed to other
stations would otherwise have to be inspected and rejected by the device driver
software, while using up bandwidth, memory space and host CPU time. Address
ltering can be implemented using the perfect address lter or the (imperfect) hash
lter. The latter produces a 6-bit hash code which can be used as an index into a
64-entry programmable hash table. In addition to the destination address, other
portions of a packet can be included in the lter decision by using a pattern match
lter. The result of the pattern-matching lter can be combined with the address
ltering to create the nal ltering result.
The receive lter has two modes:
AND mode: The AndOr bit of the RxFilterCtrl register is set to 1. The result of the
perfect address lter and the hash lter is ORed into a partial result which is
ANDed with the result of the pattern-matching lter. If the pattern-matching lter
is not enabled, the lter will not pass any packets.
OR mode: The AndOr bit of the RxFilterCtrl register is set to 0. The result of the
perfect address lter and the hash lter is ORed into a partial result which is
ORed with the result of the pattern-matching lter.