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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 13: FGPO: Fast General Purpose Output
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
13-482
4.2 Status Registers
Table 4: Status Registers
Bit
Symbol
Acces
s
Value
Description
Standard Registers
Offset 0x07,1FE0
FGPO_IR_STATUS
31:8
Reserved
R
0
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
7
BUF1_ACTIVE
R
0
1 when Buffer 1 is active
6
Reserved
R
0
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
5
MBE
R
0
Memory Bandwidth Error detected.
4
UNDERRUN
R
0
Buffer Underrun detected.
3
THRESH2_REACHED
R
0
Buffer 2 Threshold reached.
2
THRESH1_REACHED
R
0
Buffer 1 Threshold reached.
1
BUF2_DONE
R
0
Buffer 2 done.
0
BUF1_DONE
R
0
Buffer 1 done.
Offset 0x07,1FE4
FGPO_IR_ENA
31:6
Reserved
R
0
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
5
MBE_ENA
R/W
0
Memory Bandwidth Error Interrupt Enable
4
UNDERRUN_ENA
R/W
0
Buffer Underrun Interrupt Enable
3
THRESH2_REACHED_
ENA
R/W
0
Buffer 2 Threshold Interrupt Enable
2
THRESH1_REACHED_
ENA
R/W
0
Buffer 1 Threshold Interrupt Enable
1
BUF2_DONE_ENA
R/W
0
Buffer 2 done Interrupt Enable
0
BUF1_DONE_ENA
R/W
0
Buffer 1 done Interrupt Enable
Offset 0x07,1FE8
FGPO_IR_CLR
31:6
Reserved
R
0
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
5
MBE_ACK
R/W
0
Memory Bandwidth Error Interrupt Acknowledge
4
UNDERRUN_ACK
R/W
0
Buffer Underrun Interrupt Acknowledge
3
THRESH2_REACHED_
ACK
R/W
0
Buffer 2 Threshold Interrupt Acknowledge
2
THRESH1_REACHED_
ACK
R/W
0
Buffer 1 Threshold Interrupt Acknowledge
1
BUF2_DONE_ACK
R/W
0
Buffer 2 done Interrupt Acknowledge
0
BUF1_DONE_ACK
R/W
0
Buffer 1 done Interrupt Acknowledge
Offset 0x07,1FEC
FGPO_IR_SET
31:6
Reserved
R
0
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
5
MBE_SET
R/W
0
Set Memory Bandwidth Error Interrupt
4
UNDERRUN_SET
R/W
0
Set Buffer Underrun Interrupt