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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 16: Audio Input
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
16-535
The following table shows the exact bit positions assigned for a data item ‘S’.
See
Figure 5 and
Table 4 for an example of how the Audio In module registers are set
to collect 16-bit samples using the NXP SAA7366 I2S 18-bit A/D converter. (See
Section 4..) The setup assumes the SAA7366 acts as the serial master.
For example, if it were desired to use only the 12 MSBits of the A/D converter in
LEFT[15:4] being set with data bits 0..11 and LEFT[3:0] being set equal to zero.
RIGHT[15:4] is set with data bits 32..43 and RIGHT[3:0] is set to zero.
Similarly, if it was desired to use only the 12 MSBits, but send 32 bit samples to
memory, use the settings of
Table 4 with SSPOS set to 20. This results in
LEFT[31:20] being set with data bits 0...11 and LEFT[20:0] being set equal to zero.
RIGHT[31:4] is set with data bits 32...43 and RIGHT[20:0] is set to zero.
Table 3: Bit Positions Assigned for Each Data Item
Operating Mode
First Bit
Last Bit
Valid SSPOS Values
16 bit/sample, MSB-rst
S[15]
S[SSPOS]
0..15
16 bit/sample, LSB-rst
S[SSPOS]
S[15]
0..15
32 bit/sample, MSB-rst
S[31]
S[SSPOS]
0..31
32 bit/sample, LSB-rst
S[SSPOS]
S[31]
0..31
Figure 5:
Serial Frame of the SAA7366 18-Bit I2S A/D Converter (Format 2 SWS)
52
19
SCK
WS
SD
0
1
23
left n(18)
18
31 32 33 34
right n(18)
50 51
62
63
01
left n+1(18)
Table 4: Example Setup For SAA7366
Field
Value Explanation
SER_MASTER 0
SAA7366 is serial master.
SCKDIV
3
SCK set to OSCLK/4 (not needed since SER_MASTER = 0).
WSDIV
63
Serial frame length of 64 bits (not needed since SER_MASTER = 0)
POLARITY
0
Frame starts with negative WS.
FRAMEMODE
00
Take a sample of each serial frame.
VALIDPOS
n/a
Don’t care (Every frame is valid).
LEFTPOS
0
Bit position 0 is MSB of left channel and will go to LEFT[15].
RIGHTPOS
32
Bit position 32 is MSB of right channel and will go to RIGHT[15].
DATAMODE
0
MSB rst
SSPOS
0
Stop with LEFT/RIGHT[0].
CLOCK_EDGE 0
Sample WS and SD on positive SCK edges for I2S