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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 15: Audio Output
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
15-510
The OSCLK output is an accurate, programmable clock output intended to be used
as the master system clock for the external D/A subsystem. The other pins constitute
a exible serial output interface.
SCK - Serial Clock
WS - Word Select
0 = Left Channel
1 = Right Channel
SD[3:0] - Serial Data
Using the Audio Out MMIO registers, these connectors can be congured to operate
in a variety of serial interface framing modes, including but not limited to:
Standard stereo I2S (MSB rst, one bit delay from WS, left and right data in a
frame). For further details on I2S, refer to the “I2S Bus Specication” dated June 5
1996, in the Multimedia ICs Data Handbook IC22 by Philips
Semiconductors, 1998.
LSB rst with 1- to 16-bit data per channel
Table 1: Audio Out Unit External Signals[1]
Signal
Name
Type
Description
AO_OSCLK
OUT
Oversampling Clock. This output can be programmed to emit any frequency up to 50 MHz. It is
intended for use as the 256 Fs or 384 Fs oversampling clock by the external D/A conversion
subsystem.
AO_SCK
I/O
Serial Clock. When Audio Out is programmed to act as the serial interface timing slave (RESET
default), SCK acts as input. It receives the Serial Clock from the external audio D/A subsystem. The
clock is treated as fully asynchronous to the chip main clock.
When Audio Out is programmed to act as serial interface timing master, SCK acts as output. It
drives the Serial Clock for the external audio D/A subsystem. The clock frequency is a
programmable integral divide of the OSCLK frequency.
SCK is limited to the frequency of the OSCLK or lower.
AO_WS
I/O
Word Select. When Audio Out is programmed as the serial-interface timing slave (RESET default),
WS acts as an input. WS is sampled on the opposite SCK edge at which SD is asserted.
When Audio Out is programmed as serial-interface timing master, WS acts as an output. WS is
asserted on the same SCK edge as SD.
WS is the word select or frame synchronization signal from/to the external D/A subsystem. Each
audio channel receives one sample for every WS period.
WS can be set to change on OSCLK positive or negative edges by the CLOCK_EDGE bit.
AO_SD[0]
OUT
Serial Data for channel 1. Connect to stereo external audio D/A subsystem. SD[0] can be set to
change on OSCLK positive or negative edges by the CLOCK_EDGE bit.
AO_SD[1]
OUT
Serial Data for channel 2. Connect to stereo external audio D/A subsystem. SD[1] can be set to
change on OSCLK positive or negative edges by the CLOCK_EDGE bit.
AO_SD[2]
OUT
Serial Data for channel 3. Connect to stereo external audio D/A subsystem. SD[2] can be set to
change on OSCLK positive or negative edges by the CLOCK_EDGE bit.
AO_SD[3]
OUT
Serial Data for channel 4. Connect to stereo external audio D/A subsystem. SD[3] can be set to
change on OSCLK positive or negative edges by the CLOCK_EDGE bit.
[1]
These signals are external to the chip, after the pad cells.