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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 7: PCI-XIO Module
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
7-260
9
pci_err
R
0
PCI master transaction attempted when not enabled by cong
register
8
err_base10_subword
R
0
Subword attempt to base10 aperture when restrained to word only
(not used on the PNX15xx/952x Series)
7
err_base14_subword
R
0
Subword attempt to base14 aperture when restrained to word only
6
err_base18_subword
R
0
Subword attempt to base18 aperture when restrained to word only
(not used on PNX15xx/952x Series)
5
pci_mstr_parity_err
R
0
PCI master set or observed parity error (PERR)
4
err_pci_parity
R
0
PCI Detected parity error (PERR)
3
sig_serr
R
0
Signaled system error (SERR)
2
pci_r_mabort
R
0
PCI Received Master Abort
1
pci_r_tabor
R
0
PCI Received Target Abort
0
pci_s_tabort
R
0
PCI Signaled Target Abort
Offset 0x04 0FE4
PCI Interrupt Enable
31:27
Reserved
R
0
26
en_int_pcii_wr_err
R/W
0
Enable interrupt on PCI DTL initiator write error ag
25
en_int_pcii_rd_err
R/W
0
Enable interrupt on PCI DTL initiator read error ag
24
en_int_xio_wr_err
R/W
0
Enable interrupt on XIO DTL target write error ag
23
en_int_xio_rd_err
R/W
0
Enable interrupt on XIO DTL target read error ag
22
en_int_pcir_wr_err
R/W
0
Enable interrupt on mmio register DTL target write error ag
21
en_int_pcir_rd_err
R/W
0
Enable interrupt on mmio register DTL target read error
20
en_int_pwrstate_chg
R
0
Enable interrupt on change of power state register
19
Reserved
R
0
18
en_int_pci2_wr_err
R/W
0
Enable interrupt on PCI2 DTL target write error ag
17
en_int_pci2_rd_err
R/W
0
Enable interrupt on PCI2 DTL target read error ag
16
en_int_pci1_wr_err
R/W
0
Enable interrupt on PCI1 DTL target write error ag
15
en_int_pci1_rd_err
R/W
0
Enable interrupt on PCI1 DTL target read error ag
14
en_int_pci_xio_ack_don
e
R/W
0
Enable interrupt on rising edge of xio_ack done
13:12
Reserved
R
0
11
en_int_serr_seen
R/W
0
Enable interrupt on SERR observed on PCI bus
10
Reserved
R
0
9
en_int_pci_err
R/W
0
Enable interrupt on pci_err ag
8
en_int_base10_subword R/W
0
Enable interrupt on Subword Attempt to Base10 Error Status
7
en_int_base14_subword R/W
0
Enable interrupt on Subword Attempt to Base14 Error Status
6
en_int_base18_subword R/W
0
Enable interrupt on Subword Attempt to Base18 Error Status
5
en_int_pci_mstr_parity
err
R/W
0
Enable interrupt on PCI Master Parity Error
4
en_int_pci_parity
R/W
0
Enable interrupt on PCI Parity Error Status
Table 8: Registers Description
Bit
Symbol
Acces
s
Value
Description