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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 11: QVCP
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
11-406
13:8
MIDDLE_ADDR
R/W
0
Internal address in the middle Gamma Delta and base tables
7:6
Unused
-
5:0
LOWER_ADDR
R/W
0
Internal address in the lower Gamma Delta and base tables
Offset 0x10 E1F0
Shadow_Reload
31
reserved
R/W
0
should always set to 0
30
reload_mode
R/W
0
0: reload all together at line location indicated by reload_line.
1: always reload at end pixel of the layer (old mode, do not use)
29:12
Unused
R
0
11:0
reload_line
R/W
0
line count number where shadow reload occurs.
Please make sure reload line is set to a position earlier than layer
start Y position given in 0x10,E230.
Offset 0x10 E1F8
Field_Info
31:3
Unused
-
2:0
Field_ID
R
-
Field_ID is reset by disabling the screen timing generator
Field_ID is incremented with each rising edge of VSYNC and wraps
around after reaching the value 0x7 which yields a sequence of 8
elds which could be differentiated by using the Field_ID register.
Offset 0x10 E1FC
XY_Position
31
O_E_STAT
R
0
Odd/Even ag status (interlaced mode)
0 = First eld (odd/top eld)
1 = Second eld (even/bottom eld)
30:28
Unused
-
27:16
STG_Y_POS
R
-
Current vertical position of screen timing generator
15:12
Unused
-
11:0
STG_X_POS
R
-
Current horizontal position of screen timing generator
Layer & Mixer Registers
The structure of each layer function block is identical. The register for a function such as Source Address in Layer 1, has the
same structure as the corresponding register in Layer 2. Layer one starts at offset 0x200 from the QVCP base address.
Layer two starts at offset 0x400 from the QVCP base address.
Offset 0x10 E200
Layer Source Address A (Packed/Semi Planar Y)
31:28
Unused
-
27:0
Layer N Source Address
A
R/W
0
Layer N Source Data Start Address A in bytes. This sets starting
address A for data transfers from the linear Frame Buffer memory to
Layer N. For semi planar and planar modes this address points to
the Y plane.
Note: It should be aligned on a 128-byte boundary for memory
performance reasons. It has to be 8-byte aligned.
Offset 0x10 E204
Layer Source Pitch A (Packed/Semi Planar Y)
31:23
Unused
-
22:0
Layer N Pitch A
R/W
0
Layer N Source Data Pitch B in bytes. This sets pitch A for data
transfers from the linear Frame Buffer memory to Layer N. For semi
planar and planar modes this determines the pitch for the Y plane.
The value has to be rounded up to the next 64-bit word.
Table 20: QVCP 1 Registers …Continued
Bit
Symbol
Acces
s
Value
Description