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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 11: QVCP
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
11-407
Offset 0x10 E208
Layer Source Width (Packed/Semi Planar Y)
31:23
Unused
-
12:0
Layer N Source Width
R/W
0
Layer N source width in bytes. For semi planar and planar modes
this determines the source data with in bytes for the Y plane. The
value has to be rounded up to the next 64-bit word.
Offset 0x10 E20C
Layer Source Address B (Packed/Semi Planar Y)
31:28
Unused
-
27:0
Layer N Source Address
B
R/W
0
Layer N Source Data Start Address B in bytes. This sets starting
address B for data transfers from the linear Frame Buffer memory to
Layer N. For semi planar and planar modes this address points to
the Y plane.
Note: It should be aligned on a 128-byte boundary. It has to be
8-byte aligned.
Offset 0x10 E210
Layer Source Pitch B (Packed/Semi Planar Y)
31:23
Unused
-
22:0
Layer N Pitch B
R/W
0
Layer N Source Data Pitch B in bytes sets pitch B for data transfers
from the linear Frame Buffer memory to Layer N. For semi planar
and planar modes this determines the pitch for the Y plane.
The value has to be rounded up to the next 64-bit word.
Offset 0x10 E214
Dummy Pixel Count
31:8
Unused
-
7:0
DCnt
R/W
0
Number of dummy pixels to be inserted between layer video lines
Offset 0x10 E218
Layer Source Address A (Semi Planar UV)
31:28
Unused
-
27:0
Layer Source Address A
Semi Planar UV
R/W
0
Layer N Source Data Start Address A in bytes. This sets starting
address A for data transfers from the linear Frame Buffer memory to
Layer N. This Register holds the source address for the UV plane in
semi planar modes.
Note: It should be aligned on a 128-byte boundary. It has to be
8-byte aligned.
Offset 0x10 E21C
Layer Source Address B (Semi Planar UV)
31:28
Unused
-
27:0
Layer Source Address B
Semi Planar UV
R/W
0
Layer N Source Data Start Address B in bytes. This sets starting
address B for data transfers from the linear Frame Buffer memory to
Layer N. This Register holds the source address for the UV plane in
semi planar modes.
Note: It should be aligned on a 128-byte boundary. It has to be
8-byte aligned.
Offset 0x10 E220
Line Increment (Packed)
31:16
Unused
-
15:0
Line Increment Packed
R/W
0xFFFFh This register determines whether a layer line is repeatedly fetched
from memory or not.
Round Down(216/(Line Increment Packed))= #of times the same
line is fetched i.e., 0x8000H would fetch each line exactly twice (line
doubling).
Table 20: QVCP 1 Registers …Continued
Bit
Symbol
Acces
s
Value
Description