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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
23-683
0
BUSY
RO
0
When set, this bit indicates the MII Management module is currently
performing an MII Management read or write cycle.
Offset 0x07 2040
Station Address (SA0)
31:16
-
0
Unused
15:8
STATION_ADDRESS_
1ST_OCTET
R/W
0
This eld holds the rst octet of the station address.
7:0
STATION_ADDRESS__
2ND_OCTET
R/W
0
This eld holds the second octet of the station address.
Offset 0x07 2044
Station Address (SA1)
31:16
-
0
Unused
15:8
STATION_ADDRESS_
3RD_OCTET
R/W
0
This eld holds the third octet of the station address.
7:0
STATION_ADDRESS_
4TH_OCTET
R/W
0
This eld holds the fourth octet of the station address.
Offset 0x07 2048
Station Address (SA2)
31:16
-
0
Unused
15:8
STATION_ADDRESS_
5TH_OCTET
R/W
0
This eld holds the fth octet of the station address.
7:0
STATION_ADDRESS_
6TH_OCTET
R/W
0
This eld holds the sixth octet of the station address.
Offset 0x07 2100
Command Register (Command)
31:12
-
Unused
11
EnableQoS
R/W
0
When set, the arbiter operates in QoS mode, in which the real-time
transmit channel has low priority and the non-real-time channel has
high priority
10
FullDuplex
R/W
0
When set, indicates full-duplex operation.
9
RMII
R/W
0
When set, indicates RMII mode; if clear, then MII mode.
8
TxFlowControl
R/W
0
Enable IEEE 802.3 / clause 31 ow control sending pause frames in
full duplex and continuous preamble in half duplex.
7
PassRxFilter
R/W
0
When set to ‘1’, disables receive ltering, i.e., all packets received
are written to memory.
6
PassRuntFrame
R/W
0
When set to ‘1’, runt frame packets smaller than 64 bytes are
passed to memory unless they have a CRC error. If set to ‘0’, runt
frames are ltered out.
5
RxReset
WO
0
If set, reset the Receive Datapath.
4
TX RESET
WO
0
If set, reset the Transmit Datapath.
3
RegReset
WO
0
If set, reset all datapaths and the host registers. The MII Interface
must be reset separately.
2
TxRtEnable
R/W
0
Enable the real-time Transmit Datapath.
1
TxEnable
R/W
0
Enable the non-real-time Transmit Datapath.
0
RxEnable
R/W
0
Enable the Receive Datapath.
Offset 0x07 2104
Status Register (Status)
Table 2: LAN100 Registers …Continued
Bit
Symbol
Acces
s
Value
Description