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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 29: Endian Mode
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
29-813
6.4 DMA Across the MTL Bus
The 64-bit MTL bus associates byte-addresses with byte lanes in a xed manner,
independent of system endian mode, according to
Table 9.Modules that directly place data in or retrieve data from memory are DMA modules.
High bandwidth modules, or modules that require low latency access to memory,
perform DMA over the MTL Bus.
DMA modules use large (64-byte or larger) block transfers using the 8-byte lanes of
the MTL Bus within the Hub.
Modules that deal with 8, 16 or 32-bit item data sizes and connect directly to the MTL
Bus must follow the rules in
Table 10. Note in particular the bit numbers of the 16 and
32-bit data items in big-endian modes. Modules that use the DTL interface can rely
on the standard packer and DMA Endian Swap Units to accomplish the MTL Bus
rules.
16 bits
big
item #1 with address a
bit15.....................................bit0
item #2 with address a+2
bit15.....................................bit0
16 bits
little
item #2 with address a+2
bit15.....................................bit0
item #1 with address a
bit15.....................................bit0
32 bits
either
item (address a) bit31.............................................................................................bit0
Table 8: DCS Network Data Transfer Rules (32 Bits at-a-time Transfer) …Continued
Module
Item Unit
Size
System
Endian Mode
DCS_D[31:24]
DCS_D[23:16]
DCS_D[15:8]
DCS_D[7:0]
Table 9: MTL Memory Bus Byte Address
Data[63:56]
Data[55:48]
Data[47:40]
Data[39:32]
Data[31:24]
Data[23:16]
Data[15:8]
Data[7:0]
8n+7
8n+6
8n+5
8n+4
8n+3
8n+2
8n+1
8n+0
Table 10: MTL Memory Bus Item DMA Rules
Module
Item Unit
Size
System
Endian Mode
Data
[63:56]
Data
[55:48]
Data
[47:40]
Data
[39:32]
Data
[31:24]
Data
[23:16]
Data
[15:8]
Data
[7:0]
8 bits
either
item # 8
addr a+7
item #7
addr a+6
item #6
addr a+5
item #5
addr a+4
item #4
addr a+3
item #3
addr a+2
item #2
addr a+1
item #1
addr a
16 bits
big
item #4 address a+6
b7...b0 b15...b8
item #3 address a+4
b7...b0 b15...b8
item #2 address a+2
b7...b0 b15...b8
item #1 address a
b7...b0 b15...b8
16 bits
little
item #4 address a+6
b15...b8 b7...b0
item #3 address a+4
b15...b8 b...b0
item #2 address a+2
b15...b8 b7...b0
item #1 address a
b15...b8 b7...b0
32 bits
big
item #2 address a+4 b7...b0 b15...b8 b23...b16
b31...b24
item #1 address a b7..b0 b15...b8 b23...b16
b31...b24
32 bits
little
item #2 address a+4 b31...b24 b23...b16
b15...b8 b7...b0
item #1 address a b31...b24 b23...b16
b15...b8 b7...b0