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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 19: Memory Based Scaler
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
19-608
23:16
LUT_RED[X][7:0]
W
-
Red or Y
15:8
LUT_GREEN[X][7:0]
W
-
Green or U
7:0
LUT_BLUE[X][7:0]
W
-
Blue or V
Offset 0x10 C800—C9FC Coefcient Table #1 Taps 0-5 (Horizontal)
63:62
Unused
-
61:52
TAP_5[X][9:0]
W
-
Inverted coefcient, tap #5, two’s complement
51:42
TAP_4[X][9:0]
W
-
Inverted coefcient, tap #4, two’s complement
41:32
TAP_3[X][9:0]
W
-
Inverted coefcient, tap #3, two’s complement
31:30
Unused
-
29:20
TAP_2[X][9:0]
W
-
Inverted coefcient, tap #2, two’s complement
19:10
TAP_1[X][9:0]
W
-
Inverted coefcient, tap #1, two’s complement
9:0
TAP_0[X][9:0]
W
-
Inverted coefcient, tap #0, two’s complement
Offset 0x10 CA00—CBFCCoefcient Table #2 Taps 0-5 (Vertical - Luma)
63:62
Unused
-
61:52
TAP_5[X][9:0]
W
-
Inverted coefcient, tap #5, two’s complement
51:42
TAP_4[X][9:0]
W
-
Inverted coefcient, tap #4, two’s complement
41:32
TAP_3[X][9:0]
W
-
Inverted coefcient, tap #3, two’s complement
31:30
Unused
-
29:20
TAP_2[X][9:0]
W
-
Inverted coefcient, tap #2, two’s complement
19:10
TAP_1[X][9:0]
W
-
Inverted coefcient, tap #1, two’s complement
9:0
TAP_0[X][9:0]
W
-
Inverted coefcient, tap #0, two’s complement
Offset 0x10 CC00—CDFCCoefcient Table #3 Taps 0-5 (Vertical - Chroma)
63:62
Unused
-
61:52
TAP_5[X][9:0]
W
-
Inverted coefcient, tap #5, two’s complement
51:42
TAP_4[X][9:0]
W
-
Inverted coefcient, tap #4, two’s complement
41:32
TAP_3[X][9:0]
W
-
Inverted coefcient, tap #3, two’s complement
31:30
Unused
-
29:20
TAP_2[X][9:0]
W
-
Inverted coefcient, tap #2, two’s complement
19:10
TAP_1[X][9:0]
W
-
Inverted coefcient, tap #1, two’s complement
9:0
TAP_0[X][9:0]
W
-
Inverted coefcient, tap #0, two’s complement
Measurement Finish Flags Mask
Offset 0x10 CE0C
Flaggen Control Registers
31:6
Reserved
-
5
eaf_bbar_enable
R/W
0
‘1’ : meas_nish is only generated if eaf_bbar has occurred
‘0’ : meas_nish is independent from eaf_bbar
4
eaf_blklvl_enable
R/W
0
‘1’ : meas_nish is only generated if eaf_blklvl has occurred
‘0’ : meas_nish is independent from eaf_blklvl
3
eaf_histo_enable
R/W
0
‘1’ : meas_nish is only generated if eaf_histo has occurred
‘0’ : meas_nish is independent from eaf_histo
Table 8: Memory Based Scaler (MBS) Registers …Continued
Bit
Symbol
Acces
s
Value
Description