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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
23-689
31:16
-
Unused
15:0
MirrorCounterCurrent
RO
In full-duplex mode, this register represents the current value of the
datapath’s mirror counter which counts up to the value of the
MirrorCounter bits from the FlowControlCounter register. In
half-duplex mode, the datapath’s mirror counter counts until it
reaches the value of the PauseTimer bits in the FlowControlCounter
register.
Offset 0x07 21FC
Global Time-stamp Register (GlobalTimeStamp)
The global time-stamp register records the 32-bit running value of the global Time-stamp Clock. Internally, the counter is
used to generate the time-stamp eld in the transmit/receive status elds. In the real-time transmit mode, it is used as a
reference for the transmit arbiter.
31:0
GlobalTimeStamp
RO
Binary (not grey-coded) value of the global Time-stamp Counter.
Offset 0x07 2200
Receive Filter Control Register (RxFilterCtrl)
31:14
-
Unused
13
RxFilterEnWoL
R/W
When set, the result of the perfect address matching lter, the
imperfect hash lter, and the pattern match lter will generate a WoL
interrupt in case of a match.
12
MagicPacketEnWoL
R/W
When set, the result of the magic packet lter will generate a WoL
interrupt in case of a match.
11:8
PatternMatchEn
R/W
Each of the four bits enables one of the pattern-matching lter units.
The lowest order bit corresponds to lter unit 0.
7
AndOr
R/W
The AND/OR relation between the pattern-matching lter and the
accepting group of bits below. If set, the result of the pattern match
lter is ANDed with the ORed results of the accepting group below.
When set to 0, the result of the pattern-matching lter is ORed with
the ORed results of the accepting group below. See
Section 5.2.6
-
Unused
5
AcceptPerfectEn
R/W
When set to ‘1’, the packets with an address identical to the station
address are accepted.
4
AcceptMulticastHashEn
R/W
When set to ‘1’, multicast packets that pass the imperfect hash lter
are accepted.
3
AcceptUnicastHashEn
R/W
When set to ‘1’, unicast packets that pass the imperfect hash lter
are accepted.
2
AcceptMulticastEn
R/W
When set to ‘1’, all multicast packets are accepted.
1
AcceptBroadcastEn
R/W
When set to ‘1’, all broadcast packets are accepted.
0
AcceptUnicastEn
R/W
When set to ‘1’, all unicast packets are accepted.
Offset 0x07 2204
Receive Filter WoL Status Register (RxFilterWoLStatus)
The bits in this register store the cause for a WoL. Status can be cleared by writing the RxFilterWoLClear register.
31:9
-
Unused
8
MagicPacketWoL
RO
When set to ‘1’, a magic packet lter caused WoL.
7
RxFilterWoL
RO
When set to ‘1’, the receive lter caused WoL.
6
PatternMatchWoL
RO
When set to ‘1’, the pattern-matching lter caused WoL.
5
AcceptPerfectWoL
RO
When set to ‘1’, the perfect address-matching lter caused WoL.
Table 2: LAN100 Registers …Continued
Bit
Symbol
Acces
s
Value
Description