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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 9: DDR Controller
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
9-342
17:16 CPU_PREEMPT1
R/W
0x1
0x0: No preemption (once a CPU MTL command has started to
enter the DDR arbitration buffer, it will go completely into the DDR
arbitration buffer, uninterrupted by other (CPU or DMA) MTL
commands.
0x1: Preempt a CPU MTL command when it started to enter the
DDR arbitration buffer while inside of the DMA window, and is
currently active in the DMA window. The CPU MTL command will
only be interrupted by a DMA MTL command, not by another CPU
MTL command.
0x2: Undened
0x3: Preempt a CPU MTL command that is currently active in the
DMA window (independent of when it started to enter the DDR
arbitration buffer).The CPU MTL command will only be interrupted
by a DMA MTL command, not by another CPU MTL command.
Recommended value is 0.
15:2
Unused
R
-
These bits should be ignored when read, and written as 0s.
1:0
DMA_PREEMPT2
R/W
0x1
0x0: No preemption (once a DMA MTL command has started to
enter the DDR arbitration buffer, it will go completely into the DDR
arbitration buffer, uninterrupted by other (CPU or DMA) MTL
commands.
0x1: Preempt a DMA MTL command when it started to enter the
DDR arbitration buffer while inside of the CPU window, and is
currently active in the CPU window. The DMA MTL command will
only be interrupted by a CPU MTL command, not by another DMA
MTL command.
0x2: Undened
0x3: Preempt a DMA MTL command that is currently active in the
CPU window (independent of when it started to enter the DDR
arbitration buffer).The DMA MTL command will only be interrupted
by a CPU MTL command, not by another DMA MTL command.
If enabled recommended value is 3.
1 The preemption eld determines the aggressiveness with which MTL commands are preempted when they are active in a
window that was not meant for the MTL command. Value 0 represents low aggressiveness, value 0x1 represents medium
aggressiveness, and value 0x3 represents high aggressiveness. The more aggressive, the better the time multiplexing by
means of windows is accomplished. However, aggressive preemption may result in lower overall bandwidth.
2 See above footnote.
Offset 0x06 5184
ARB_HRT_WINDOW
31:16
Unused
R
-
These bits should be ignored when read, and written as 0s.
15:0
WINDOW
R/W
0x003f
Window size for Hard Real-Time (HRT) MTL requests (in terms of
clock cycles). Add 1 for the real effective window size.
Offset 0x06 5188
ARB_CPU_WINDOW
31:16
Unused
R
-
These bits should be ignored when read, and written as 0s.
15:0
WINDOW
R/W
0x003F
Window for Central Processor Unit (CPU) MTL requests (in terms of
clock cycles). Add 1 for the real effective window size
Offset 0x06 51C0
ARB_CPU_LIMIT
31:16
Unused
R
-
These bits should be ignored when read, and written as 0s.
Table 9: Register Description
Bit
Symbol
Access
Value
Description