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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
23-682
Offset 0x07 2020
MII Mgmt Conguration (MCFG)
31:16
-
0
Unused
15
RESET_MII_MGMT
R/W
0
For more information refer to the MII Interface documentation
[2].14:5
-
0
Unused
4:2
CLOCK_SELECT
R/W
0
This eld is used by the clock divide logic to create the MII
Management Clock (MDC) which IEEE 802.3u denes to be no
faster than 2.5 MHz. Some PHYs support clock rates up to 12.5
MHz, however. For more information refer to the MII Interface
1
SUPPRESS_
PREAMBLE
R/W
0
For more information refer to the MII Interface documentation
[2].0
SCAN_INCREMENT
R/W
0
For more information refer to the MII Interface documentation
[2].Offset 0x07 2024
MII Mgmt Command (MCMD)
31:2
-
0
Unused
1
SCAN
R/W
0
This bit causes the MII Management module to perform read cycles
continuously. This is useful for monitoring the Link Fail timer, for
example.
0
READ
R/W
0
This bit causes the MII Management module to perform a single
read cycle. The read data is returned in Register MRDD (MII Mgmt
Read Data).
Offset 0x07 2028
MII Mgmt Address (MADR)
31:13
-
0
Unused
12:8
PHY_ADDRESS
R/W
0
This eld represents the 5-bit PHY address eld of Management
cycles. Up to 31 PHYs can be addressed (0 is reserved).
7:5
-
0
Unused
4:0
REGISTER_ADDRESS
R/W
0
This eld represents the 5-bit Register Address eld of
Management cycles. Up to 32 registers can be accessed.
Offset 0x07 202C
MII Mgmt Write Data (MWTD)
31:16
-
0
Unused
15:0
WRITE_DATA
WO
0
When written, an MII Management write cycle is performed using
the 16-bit data and the pre-congured PHY and Register addresses
from Register (0x0A).
Offset 0x07 2030
MII Mgmt Read Data (MRDD)\
31:16
-
0
Unused
15:0
READ_DATA
RO
0
Following a MII Management Read Cycle, the 16-bit data can be
read from this location.
Offset 0x07 2030
MII Mgmt Read Data (MRDD)\
31:3
-
0
Unused
2
NOT_VALID
RO
0
When set, this bit indicates the MII Management Read cycle has not
completed, and the Read Data is not yet valid.
1
SCANNING
RO
0
When set, this bit indicates a scan operation (continuous MII
Management Read cycles) is in progress.
Table 2: LAN100 Registers …Continued
Bit
Symbol
Acces
s
Value
Description