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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
23-680
6:0
BACK_TO_BACK_
INTER_PACKET_GAP
R/W
0
This is a programmable eld representing the nibble time offset of
the minimum possible period between the end of any transmitted
packet, to the beginning of the next. In full-duplex mode, the
register value should be the desired period in nibble times minus 3.
In half-duplex mode, the register value should be the desired period
in nibble times minus 6. In full-duplex, the recommended setting is
0x15 (21 decimal), which represents the minimum IPG of 0.96 ms
(in 100 Mb/s) or 9.6 ms (in 10 Mb/s). In half-duplex the
recommended setting is 0x12 (18 decimal), which also represents
the minimum IPG of 0.96 ms (in 100 Mb/s) or 9.6 ms (in 10 Mb/s).
Offset 0x07 200C
Non Back-to-Back Inter-Packet-Gap Register (IPGR)
31:15
-
0
-
Unused
14:8
NON_BACK_TO_
BACK_INTER_
PACKET_GAP_PART_1
0
R/W
This is a programmable eld representing the optional carrierSense
window referenced in IEEE 802.3 section 4.2.3.2.1 titled “Carrier
Deference”. If carrier is detected during the timing of IPGR1, the
MAC defers to carrier. If, however, carrier becomes active after
IPGR1, the MAC continues timing IPGR2 and transmits, knowingly
causing a collision, thus ensuring fair access to the medium. Its
range of values is 0x0 to IPGR2.
7
-
0
-
Unused
6:0
NON_BACK_TO_
BACK_INTER_
PACKET_GAP_PART_2
0x12
R/W
This is a programmable eld representing the Non-Back-to-Back
Inter-Packet-Gap. The default is 0x12 (18 decimal), which
represents the minimum IPG of 0.96 ms (in 100 Mb/s) or 9.6 ms (in
10 Mb/s).
Offset 0x07 2010
Collision Window / Retry Register (CLRT)
31:14
-
0
Unused
13:8
COLLISION_WINDOW
R/W
0x37
This is a programmable eld representing the slot time or collision
window during which collisions occur in properly congured
networks. Since the collision window starts at the beginning of
transmission, the preamble and SFD is included. Its default of 0x37
(55 decimal) corresponds to the count of frame bytes at the end of
the window.
7:4
-
0
Unused
3:0
RETRANSMISSION_
MAXIMUM
R/W
0xF
This is a programmable eld specifying the number of
retransmission attempts following a collision before aborting the
packet because of excessive collisions. The Standard species the
attemptLimit to be 0xF (15 decimal).
Offset 0x07 2014
Maximum Frame Register (MAXF)
31:16
-
0
Unused
15:0
MAXIMUM_FRAME_
LENGTH
R/W
0x0600
This eld’s reset value is 0x0600, which represents a maximum
receive frame of 1536 octets. An untagged maximum size Ethernet
frame is 1518 octets. A tagged frame adds four octets for a total of
1522 octets. If a shorter maximum length restriction is desired,
program this 16-bit eld.
Offset 0x07 2018
PHY Support Register (SUPP)
The SUPP register is only relevant if an SMII, RMII, PMD or ENDEC interface is provided to the PHY.
31:16
-
0
Unused
Table 2: LAN100 Registers …Continued
Bit
Symbol
Acces
s
Value
Description