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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 25: I2C Interface
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
25-768
When the CPU writes to DAT, the buffer is loaded with the contents of DAT(7) which is
the rst bit to be transmitted to the SDA line. After nine serial clock pulses, the eight
bits in DAT will have been transmitted to the SDA line, and the acknowledge bit will be
present in ACK. Note that the eight transmitted bits are shifted back into DAT.
Bit [7:3]: STA Status register
STA is a read-only special function register. Writing to this register has no affect. The
three least signicant bits are always zero. The bits 7-3 contain the status code.
There are 26 possible status codes. When STA contains 0xF8, no relevant state
information is available and no serial interrupt is requested. Reset initializes STA to
0xF8. All other STA values correspond to dened IIC module states.
See the last row of
Table 5 for an explanation of the terms used.
Table 4: IIC Registers
Bit
Symbol
Acces
s
Value
Description
Offset 0x04 5008
I2C STATUS REGISTER
31:8
Unused
-
Ignore upon read. Write as zeroes.
7:3
STA
R
0
Indicates the status of the IIC module.
2:0
Unused
-
Ignore upon read. Write as zeroes.
Table 5: Status Codes
Status
Code
STA
Bus/Module
Status
Application Software Response
Next Action Taken
To/From DAT
To CON
STA
STO
SI
AA
0x00
Bus Error
No DAT Action 0
1
0
X
HW will enter the “not addressed” slave
mode.
0x08
A Start condition
has been
transmitted
Load SLA+W
X
0
X
SLA+W will be transmitted, ACK bit will be
received (I2C bus module will be switched to
MST/TRX mode).
Load SLA+R
X
0
X
SLA+R will be transmitted, ACK bit will be
received (I2C bus module will be switched to
MST/REC mode).
0x10
A repeated Start
condition has been
transmitted
Load SLA+W
X
0
X
SLA+W will be transmitted, ACK bit will be
received (I2C bus module will be switched to
MST/TRX mode).
Load SLA+R
X
0
X
SLA+R will be transmitted, ACK bit will be
received (I2C bus module will be switched to
MST/REC mode).
0x18
SLA+W has been
transmitted; ACK
has been received
Load data byte 0
0
X
Data byte will be transmitted; ACK bit will be
received.
no DAT action
1
0
X
Repeat START will be transmitted
no DAT action
0
1
0
X
STOP condition will be transmitted; STOP
ag will be reset.
no DAT action
1
0
X
STOP condition followed by a START
condition will be transmitted; STO ag will
be reset.