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NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 7: PCI-XIO Module
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
7-242
The following table is a summary of all the registers in this module.
0x000C
Latency Timer/ Cache
Line size
Latency Timer, Cache Line Size.
0x0010
Base Address 10
Base Address, memory
0x0014
Base Address 14
Base Address, memory — MMIO
0x0018
Base Address 18
Base Address, memory — XIO
0x001—
0028
Reserved
0x002C
Subsystem ID
Subsystem ID and Subsystem Vendor ID
0x0030
Reserved
0x0034
Capability Pointer
Capabilities Pointer Register
0x0038
Reserved
0x003C
INTR
Interrupt Line, Interrupt Pin, Min_Gnt, MAX_Lat
0x0040
pmc
Power management Capability
0x0044
pwr_state
Power Management control
Table 7: PCI Conguration Register Summary …Continued
Bit
Symbol
Description
Table 8: Registers Description
Bit
Symbol
Acces
s
Value
Description
PCI Control Registers
This register must be initialized before any PCI cycles will be entertained. The boot loader is expected to load the values at
boot time. Write once by boot loader, otherwise read only. Because this register is “written once” the bit elds are designated
“R/W1.” An unlock is available to update this register if necessary. A write of “CA” to bits [7:0] of the unlock_setup register
will allow one additional write to the setup register before locking again
Offset 0x04 0010
PCI Setup
31
Reserved
R
0
30
dis_reqgnt
R/W1
0
Disable use of REQ/GNT when using internal arbiter. These pins
may be released for other uses when using an internal arbiter and
no external PCI masters are used in the system.
29
dis_reqgnt_a
R/W1
0
Disable use of REQ_A/GNT_A when using internal arbiter. These
pins are not used when using an external harborer.
28
dis_reqgnt_b
R/W1
0
Disable use of REQ_B/GNT_B when using internal arbiter. These
pins are not used when using an external arbiter.
27
d2_support
R/W1
1
Support for D2 power state
26
d1_support
R/W1
1
Support for D1 power state
25
Reserved
R/W1
0
24
en_ta
R/W1
0
Terminate restricted access attempt with target abort (otherwise,
ignore writes, return 0 on read).
23
en_pci2mmi
R/W1
1
Enable memory hwy interface.
22
en_xio
R/W1
1
Enable XIO functionality.
21
base18_prefetchable
R/W1
0
PCI base address 18 is a prefetchable memory aperture.